r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1280

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

24. Multimedia Card Interface (MMCIF)
24.6.2
To transfer data to FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC. Then,
start transfer to the card after a FIFO ready interrupt. Figure 24.26 to 24.28 shows the operational
flow for a write sequence.
• Clear FIFO.
• Transmit write command.
• Make settings in DMACR, and set write data to FIFO.
• Check whether data exceeding the DMACR setting condition is written to FIFO by a FIFO
• Confirm that the DMAC transfer is completed and be sure to clear the DMAEN bit in
• Set the CMDOFF bit to 1 if a CRC error (CRCERI) or a data timeout error (DTERI) occurs in
• Set the CMDOFF bit to 1, clear FIFO, and clear DMACR to H'00 if a CRC error (CRCERI) or
When using DMA, an inter-block interrupt can be processed by hardware in pre-defined multiple
block transfer by setting the AUTO bit in DMACR to 1. Figure 24.29 shows the operational flow
for a pre-defined multiple block write sequence using auto-mode.
• Clear FIFO.
• Set the block number to TBNCR.
• Set the CMDSTART bit in CMDSTRT to 1 and begin command transmission.
• Command response is received from the card.
• A command timeout error (CTERI) is detected if a command response is not received from the
• Set DMACR and write data in FIFO.
• Confirm that the DMA transfer has been completed and clear the DMAEN bit in DMACR to
• Detect the end of the command sequence by poling the BUSY flag in CSTR or through the
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ready interrupt (FRDYI) or DMAC has transferred all data to FIFO. Then set 1 to the
DATAEN bit in OPCR to start write-data transmission.
In a write to the card by stream transfer, the MMCIF continues data transfer to the card even
after a FIFO empty interrupt is detected. Therefore, complete the write sequence after at least
24 card clock cycles.
DMACR to 0.
the command response reception.
a data timeout error (DTERI) occurs in the write data transmission.
card.
0.
pre-defined multiple block transfer end flag (BTI).
Operation in Write Sequence