r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 516

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

12. DDR2-SDRAM Interface (DBSC2)
12.4.4
The SDRAM configuration setting register (DBCONF) is a readable/writable register. It is
initialized only upon power-on reset.
Rev.1.00 Jan. 10, 2008 Page 486 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 24 ⎯
23 to 16 SPLIT7 to
R/W:
R/W:
BIt:
BIt:
SDRAM Configuration Setting Register (DBCONF)
Bit Name
SPLIT0
31
15
⎯
⎯
R
R
0
0
30
⎯
14
⎯
R
R
0
0
29
⎯
13
⎯
Initial
Value
All 0
1001 1010 R/W
R
R
0
0
28
12
⎯
⎯
R
R
0
0
27
11
⎯
⎯
R
R
0
0
R/W
R
26
10
⎯
⎯
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
Memory Configuration Select Bits
These bits select the memory configuration to be used.
These are used in combination with the BASFT and the
BWIDTH bits. For details on address multiplexing, refer
to section 12.5.6, Regarding Address Multiplexing.
1001 1010: 256-Mbit product (16M × 16 bits)
1001 1011: 512-Mbit product (32M × 16 bits)
1101 1011: 1-Gbit product (64M × 16 bits)
1110 0011: 2-Gbit product (128M × 16 bits)
0001 1011: 256-Mbit product (32M × 8 bits)
0010 0011: 512-Mbit product (64M × 8 bits)
0110 0011: 1-Gbit product (128M × 8 bits)
0110 1011: 2-Gbit product (256M × 8 bits)
Other than above: Setting prohibited (If specified,
BASFT1
R/W
25
⎯
R
0
9
0
BASFT0
R/W
24
⎯
R
0
8
0
SPILT7
R/W
23
⎯
R
1
7
0
SPILT6
R/W
correct operation cannot be
guaranteed.)
22
⎯
R
0
6
0
SPILT5
R/W
21
⎯
R
0
5
0
SPILT4
R/W
20
⎯
R
1
4
0
SPILT3
R/W
19
⎯
R
1
3
0
SPILT2
R/W
18
⎯
R
0
2
0
SPILT1
BWID
R/W
R/W
TH1
17
1
1
0
SPILT0
BWID
R/W
R/W
TH0
16
0
0
1