r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 884

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

19. Display Unit (DU)
19.3.5
The display unit interrupt enable register (DIER) is a register which enables interrupts to the CPU
the causes of which are internal states of the display unit (DU) reflected in DSSR. When bits are
set in this register, if bits in the same bit positions in DSSR are set, an interrupt is issued to the
CPU.
Internal update:
Internal update:
Rev.1.00 Jan. 10, 2008 Page 854 of 1658
REJ09B0261-0100
Bit
9
8
7 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Display Unit Interrupt Enable Register (DIER)
Bit Name
RICL
HBCL
⎯
R/W
TVE
31
15
—
R
0
0
R/W
FRE
30
—
14
R
0
0
Undefined W
Undefined W
All 0
Initial
Value
29
13
—
—
R
R
0
0
28
12
—
—
R
R
0
0
R/W
R
R/W
VBE
27
11
—
R
0
0
Internal
Update
None
None
⎯
26
10
—
—
R
R
0
0
R/W
RIE
25
—
R
0
9
0
Description
Vertical Blanking Flag Clear
0: The RINT flag in DSSR is not changed.
1: The RINT flag in DSSR is cleared to 0.
Vertical Blanking Flag Clear
0: The HBK flag in DSSR is not changed.
1: The HBK flag in DSSR is cleared to 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
HBE
24
—
R
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
16
—
—
R
R
0
0
0