r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 629

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Part Number
Manufacturer
Quantity
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Part Number:
r8a77850anbgV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
9
8
7
Bit Name
TMTOI
MDEI
APEDI
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Target Memory Read Retry Timeout Interrupt
Indicates that the master did not perform retry
processing within 2
PCIC is a target. This bit is detected only for memory
read transfers.
0: A target memory read retry timeout interrupt was
1: A target memory read retry timeout interrupt was
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
Master Function Disable Error Interrupt
Indicates that the PCIC attempted to operate as a
master (PIO or DMA transfer) although bit 2 (BM) in
PCICMD is cleared to 0 and operation as a bus
master is disabled.
0: A master function disable error interrupt was not
1: A master function disable error interrupt was
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
Address Parity Error Detection Interrupt
Indicates that an address parity error was detected.
Note: An address parity error is detected only when
0: An address parity error interrupt was not
1: An address parity error interrupt was generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
generated
not generated
generated
generated
generated
both of the bits 8 (SERRE) and 6 (PER) in
PCICMD are set to 1.
Rev.1.00 Jan. 10, 2008 Page 599 of 1658
15
clocks in PCICLK when the
13. PCI Controller (PCIC)
REJ09B0261-0100

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