r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 996
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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19. Display Unit (DU)
19.5.5
The display unit (DU) enables selection of output timing, with respect to the output dot clock, of
the various output signals (the four sync signals HSYNC, VSYNC, CSYNC, ODDF, as well as
DISP, CDE, CLAMP, DE, digital RGB signals). Timing is selected by setting OTAR.
Table 19.16 Output Signal Timing Setting Parameters
Rev.1.00 Jan. 10, 2008 Page 966 of 1658
REJ09B0261-0100
Bit Name in OTAR
SYNCA
DISPA
CDEA
DRGBA
CLAMPA
DEA
Note: Timing charts other than this chart in this section are all provided on basic timing.
DCLKOUT
Reference timing
Output Signal Timing Adjustment
Figure 19.19 Adjustable Range of Output Timing
Description
Sets output timing of the HSYNC, VSYNC, CSYNC, ODDF signal
Sets output timing of the DISP signal
Sets output timing of the CDE signal
Sets output timing of digital RGB signal
Sets output timing of the CLAMP signal
Sets output timing of the DE signal
Register value
(Initial value)
B'000
B'100
B'101
B'001
B'110
B'010
B'111
B'011
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