DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 112

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 8-2:
DS70652C-page 112
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-0
Note 1:
R/W-0
ROI
U-0
—
2:
3:
This bit is cleared when the ROI bit is set and an interrupt occurs.
If DOZEN = 1, writes to DOZE<2:0> are ignored.
If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored.
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: Processor Clock Reduction Select bits
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
DOZEN: DOZE Mode Enable bit
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio forced to 1:1
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divide by 256
110 = FRC divide by 64
101 = FRC divide by 32
100 = FRC divide by 16
011 = FRC divide by 8
010 = FRC divide by 4
001 = FRC divide by 2
000 = FRC divide by 1 (default)
Unimplemented: Read as ‘0’
R/W-0
U-0
—
CLKDIV: CLOCK DIVISOR REGISTER
CY
CY
CY
CY
CY
CY
CY
CY
/128
/64
/32
/16
/8 (default)
/4
/2
/1
DOZE<2:0>
W = Writable bit
‘1’ = Bit is set
R/W-1
U-0
—
(2,3)
R/W-1
(1,2,3)
U-0
Preliminary
—
DOZEN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
(1,2,3)
(2,3)
R/W-0
U-0
—
© 2011 Microchip Technology Inc.
FRCDIV<2:0>
x = Bit is unknown
R/W-0
U-0
—
R/W-0
U-0
—
bit 8
bit 0