DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 75

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to
minimum pulse width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.4.1
Many systems have external supervisory circuits that
generate Reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.4.2
When using the internal power supervisory circuit to
Reset the device, the external Reset pin (MCLR)
should be tied directly or resistively to V
the MCLR pin will not be used to generate a Reset. The
external Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.5
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a spe-
cial Reset state. This Reset state will not re-initialize the
clock. The clock source in effect prior to the RESET
instruction will remain. SYSRST is released at the next
instruction cycle, and the Reset vector fetch will
commence.
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate the
software Reset.
6.6
Whenever a Watchdog Time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control (RCON<4>) register is set to indicate the
Watchdog Reset. Refer to
Timer (WDT)”
Reset.
© 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Section 26.0 “Electrical Characteristics”
External Reset (EXTR)
Software RESET Instruction (SWR)
Watchdog Time-out Reset (WDTO)
EXTERNAL SUPERVISORY
CIRCUIT
INTERNAL SUPERVISORY CIRCUIT
for more information on Watchdog
Section 23.4 “Watchdog
DD
. In this case,
Preliminary
for
6.7
If a lower-priority hard trap occurs while a higher-prior-
ity trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to
more information on trap conflict Resets.
6.8
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell dis-
turbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
The Configuration Mismatch Flag (CM) bit in the Reset
Control (RCON<9>) register is set to indicate the
configuration mismatch Reset. Refer to
“I/O Ports”
mismatch Reset.
6.9
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control (RCON<14>)
register is set to indicate the illegal condition device
Reset.
6.9.1
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 0x3F,
which is an illegal opcode value.
Note:
Trap Conflict Reset
Configuration Mismatch Reset
Illegal Condition Device Reset
The configuration mismatch feature and
associated Reset flag is not available on
all devices.
ILLEGAL OPCODE RESET
for more information on the configuration
Section 7.0 “Interrupt Controller”
DS70652C-page 75
Section 10.0
for