DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 4

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Timers/Capture/Compare/PWM:
• Timer/Counters, up to three 16-bit timers:
• Input Capture (up to three channels):
• Output Compare (up to two channels):
• Hardware Real-Time Clock and Calendar
Digital I/O:
• Peripheral Pin Select functionality
• Up to 21 programmable digital I/O pins
• Wake-up/Interrupt-on-Change for up to 21 pins
• Output pins can drive from 3.0V to 3.6V
• Up to 5.5V output with open drain configuration on
• All digital input pins are 5V tolerant
• Up to 8 mA sink on designated pins
Communication Modules:
• 4-wire SPI:
• I
• UART:
DS70652C-page 4
- Can pair up to make one 32-bit timer
- One timer runs as Real-Time Clock with
- Programmable prescaler
- Capture on up, down, or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
(RTCC):
- Provides clock, calendar and alarm function
5V tolerant pins
- Framing supports I/O interface to simple
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN 2.0 bus support
- IrDA
- High-Speed mode
- Hardware Flow Control with CTS and RTS
2
C™:
external 32.768 kHz oscillator
codecs
sampling modes
®
encoding and decoding in hardware
Preliminary
Interrupt Controller:
• 5-cycle latency
• Up to 23 available interrupt sources
• Up to three external interrupts
• Seven programmable priority levels
• Four processor exceptions
High-Performance MCU CPU Features:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit-wide data path
• 24-bit-wide instructions
• Linear program memory addressing up to 4M
• Linear data memory addressing up to 64 Kbytes
• 73 base instructions: mostly one word/one cycle
• Flexible and powerful indirect addressing mode
• Software stack
• 16 x 16 integer multiply operations
• 32/16 and 16/16 integer divide operations
• Up to ±16-bit shifts
Additional High-Performance DSC CPU
Features:
• 11 additional instructions
• Two 40-bit accumulators with rounding and
• Additional flexible and powerful addressing
• Single-cycle multiply and accumulate:
• Shifts for up to 40-bit data
• 16 x 16 fractional multiply/divide operations
Packaging:
• 18-pin PDIP/SOIC
• 20-pin PDIP/SOIC/SSOP
• 28-pin SPDIP/SOIC/SSOP/QFN
• 28-pin QFN: 6x6 mm
• 36-pin TLA: 5x5 mm
instruction words
saturation options
modes:
- Modulo
- Bit-reversed
- Accumulator write back for DSP operations
- Dual data fetch
Note:
See
features per device.
Table 1
© 2011 Microchip Technology Inc.
for the list of peripheral