DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 230

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DSPIC33FJ16MC101T-I/SS

Manufacturer Part Number
DSPIC33FJ16MC101T-I/SS
Description
16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ16MC101T-I/SS

Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
TABLE 23-3:
DS70652C-page 230
WDTPOST<3:0>
ICS<1:0>
PWMPIN
Bit Field
PLLKEN
ALTI2C
HPOL
LPOL
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
RTSP Effect
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
0001 = 1:2
0000 = 1:1
PLL Lock Enable bit
1 = Clock switch to PLL will wait until the PLL lock signal is valid
0 = Clock switch will not wait for the PLL lock signal
Alternate I
1 = I
0 = I
ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
Motor Control PWM Module Pin Mode bit
1 = PWM module pins controlled by PORT register at device Reset
0 = PWM module pins controlled by PWM module at device Reset
Motor Control PWM High Side Polarity bit
1 = PWM module high side output pins have active-high output polarity
0 = PWM module high side output pins have active-low output polarity
Motor Control PWM Low Side Polarity bit
1 = PWM module low side output pins have active-high output polarity
0 = PWM module low side output pins have active-low output polarity
2
2
(tri-stated)
(configured as output pins)
C mapped to SDA1/SCL1 pins
C mapped to ASDA1/ASCL1 pins
2
C™ pins
Preliminary
Description
© 2011 Microchip Technology Inc.

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