DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 39

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2
The
dsPIC33FJ16MC101/102 CPU has a separate 16-bit-
wide data memory space. The data space is accessed
using separate Address Generation Units (AGUs) for
read and write operations. The data memory maps is
shown in
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see
Program Memory Using Program Space
Microchip
dsPIC33FJ16MC101/102 devices implement up to
1 Kbyte of data memory. Should an EA point to a loca-
tion outside of this area, an all-zero word or byte will be
returned.
4.2.1
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2
To maintain backward compatibility with PIC
devices and improve data space memory usage
efficiency,
dsPIC33FJ16MC101/102 instruction set supports both
word and byte operations. As a consequence of byte
accessibility, all effective address calculations are
internally scaled to step through word-aligned memory.
For example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] will result in
a value of Ws + 1 for byte operations and Ws + 2 for
word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decoding
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
© 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Data Address Space
Figure
DATA SPACE WIDTH
DATA MEMORY ORGANIZATION
AND ALIGNMENT
the
dsPIC33FJ16GP101/102
4-3.
dsPIC33FJ16GP101/102
Section 4.6.3 “Reading Data from
dsPIC33FJ16GP101/102
Visibility”).
®
MCU
and
and
and
Preliminary
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction in progress is completed. If the error
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then exe-
cuted, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternately, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the
appropriate address.
4.2.3
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers
dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/
102 core and peripheral modules for controlling the
operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.4
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV class of instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode with a working register
as an address pointer.
Note:
SFR SPACE
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and pin-
out
information.
NEAR DATA SPACE
(SFRs).
diagrams
These
for
are
DS70652C-page 39
used
device-specific
by
the