DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 193

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 19-1:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-10
bit 9-8
bit 7-5
bit 4
bit 3
bit 2
bit 1
Note 1:
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
ADON
R/W-0
R/W-0
Available only on dsPIC33FJ16MC101/102 devices.
ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
FORM<1:0>: Data Output Format bits
11 = Signed fractional (D
10 = Fractional (D
01 = Signed integer (D
00 = Integer (D
SSRC<2:0>: Sample Clock Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU
101 = Reserved
100 = Reserved
011 = Motor Control PWM interval ends sampling and starts conversion
010 = GP timer 3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing sample bit ends sampling and starts conversion
Unimplemented: Read as ‘0’
SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x)
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
0 = Samples multiple channels individually in sequence
ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion. SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
SAMP: ADC Sample Enable bit
1 = ADC sample-and-hold amplifiers are sampling
0 = ADC sample-and-hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,
automatically cleared by hardware to end sampling and start conversion.
SSRC<2:0>
R/W-0
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
U-0
—
AD1CON1: ADC1 CONTROL REGISTER 1
HC = Cleared by hardware
‘1’ = Bit is set
W = Writable bit
OUT
ADSIDL
R/W-0
R/W-0
OUT
= 0000 00dd dddd dddd)
= dddd dddd dd00 0000)
OUT
OUT
= ssss sssd dddd dddd, where s = .NOT.d<9>)
= sddd dddd dd00 0000, where s = .NOT.d<9>)
Preliminary
U-0
U-0
—
—
HS = Set by hardware C = Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SIMSAM
R/W-0
U-0
—
ASAM
R/W-0
U-0
—
(1)
x = Bit is unknown
HC,HS
R/W-0
R/W-0
SAMP
FORM<1:0>
DS70652C-page 193
HC, HS
DONE
R/W-0
R/C-0
bit 8
bit 0