DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 76

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
6.9.2
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.9.3
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a pro-
tected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
TABLE 6-3:
DS70652C-page 76
Note: All Reset flag bits can be set or cleared by user software.
TRAPR (RCON<15>)
IOPWR (RCON<14>)
SLEEP (RCON<3>)
WDTO (RCON<4>)
EXTR (RCON<7>)
SWR (RCON<6>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
CM (RCON<9>)
UNINITIALIZED W REGISTER
RESET
SECURITY RESET
Flag Bit
RESET FLAG BIT OPERATION
W register access or Security Reset
Illegal opcode or uninitialized
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
Configuration Mismatch
Preliminary
Trap conflict event
RESET instruction
WDT Time-out
MCLR Reset
POR, BOR
Set by:
POR
6.10
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Table 6-3
operation.
Note:
Using the RCON Status Bits
provides a summary of Reset flag bit
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
CLRWDT instruction, POR, BOR
© 2011 Microchip Technology Inc.
PWRSAV instruction,
Cleared by:
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR
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