DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 175

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.0
The Inter-Integrated Circuit™ (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
The I
• The SCLx pin is clock
• The SDAx pin is data
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
© 2011 Microchip Technology Inc.
modes of operation.
master and slaves
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
collision and arbitrates accordingly
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
2
Note 1: This data sheet summarizes the features
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7-bit and 10-bit addresses
C Master mode supports 7-bit and 10-bit addresses
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
2
2
C module has a 2-pin interface:
C module offers the following key features:
2: Some registers and associated bits
INTER-INTEGRATED CIRCUIT™
(I
2
C™)
of the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 19. “Inter-Inte-
grated Circuit™ (I
the
Reference Manual”, which is available
from
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
the
“dsPIC33F/PIC24H
2
Microchip
C serial communication
2
2
C™) module provides
C™)” (DS70195) in
2
C port can be
family
web
Family
site
Preliminary
of
in
17.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7-bit and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, refer to the Microchip web site
(www.microchip.com) for the latest “dsPIC33F/PIC24H
Family Reference Manual” sections.
17.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
• I2CxRSR is the shift register used for shifting data
• I2CxRCV is the receive buffer and the register to
• I2CxTRN is the transmit register to which bytes
• I2CxADD register holds the slave address
• ADD10 status bit indicates 10-bit Address mode
• I2CxBRG acts as the Baud Rate Generator (BRG)
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
which data bytes are written, or from which data
bytes are read
are written during a transmit operation
reload value
2
2
2
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7-bit or 10-bit address
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70652C-page 175