DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 312

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Revision C (June 2011)
This revision includes the following global update:
• All JTAG references have been removed
All other major changes are referenced by their
respective section in
In addition, minor text and formatting changes were
incorporated throughout the document.
TABLE A-2:
DS70652C-page 312
High-Performance, Ultra Low Cost
16-bit Digital Signal Controllers
Section 1.0 “Device Overview”
Section 4.0 “Memory Organization”
Section 6.0 “Resets”
Section 8.0 “Oscillator Configuration”
Section 15.0 “Motor Control PWM
Module”
Section 19.0 “10-bit Analog-to-Digital
Converter (ADC)”
Section 22.0 “Charge Time
Measurement Unit (CTMU)”
Section Name
MAJOR SECTION UPDATES
Table
A-2.
The TMS, TDI, TDO, and TCK pin names were removed from these pin
diagrams:
• 28-pin SPDIP/SOIC/SSOP
• 28-pin QFN
• 36-pin TLA
Updated the Buffer Type to Digital for the CTED1 and CTED2 pins (see
Table
Updated the SFR Address for IC2CON, IC3BUF, and IC3CON in the Input
Capture Register Map (see
Added the VREGS bit to the RCON register in the System Control Register
Map (see
Added the VREGS bit to the RCON register (see
Updated the definition for COSC<2:0> = 001 and NOSC<2:0> = 001 in
the OSCCON register (see
Updated the title for
language.
Added
protected register unlock and fault clearing sequence.
Updated the CH0 section and added Note 2 in both ADC block diagrams
(see
Updated the multiplexer values in the ADC Conversion Clock Period Block
Diagram (see
Added the 01110 bit definitions and updated the 01101 bit definitions for
the CH0SB<4:0> and CH0SA<4:0> bits in the AD1CHS0 register (see
Register
Removed Section 22.1 “Measuring Capacitance”, Section 22.2 “Measuring
Time”, and Section 22.3 “Pulse Generation and Delay”
Updated the key features.
Added the CTMU Block Diagram (see
Updated the ITRIM<5:0> bit definitions and added Note 1 to the CTMU
Current Control register (see
Figure 19-1
1-1).
Example
Preliminary
19-5).
Table
Figure
4-27).
15-2, which provides a C code version of the write-
and
Example 15-1
19-3.
Figure
Update Description
Register
Table
19-2).
Register
4-7).
to include a reference to the Assembly
8-1).
22-3).
Figure
© 2011 Microchip Technology Inc.
22-1).
Register
6-1).