DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 228

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The Configuration Shadow register map is shown in
TABLE 23-1:
The Configuration Flash Words map is shown in
TABLE 23-2:
CONFIG2 002BFC
CONFIG1 002BFE
Legend:
Note
Legend:
Note
Address
F8000A
F8000C
F8000E
Name
F80004
F80006
F80008
File
1:
2:
3:
4:
1:
2:
3:
Addr.
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
— = unimplemented, read as ‘1’.
During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
This bit is reserved on dsPIC33FJ16GP101/102 devices and reads as ‘1’.
This bit is reserved; program as ‘0’.
This bit is reserved for use by development tools and must be programmed as ‘1’.
— = unimplemented, read as ‘1’.
These bits are only available on dsPIC33FJ16MC101/102 devices.
This bit is reserved for use by development tools.
This bit is reserved; program as ‘0’.
Name
Bits 23-16
CONFIGURATION SHADOW REGISTER MAP
CONFIGURATION FLASH WORDS
—
—
PWMPIN
Reserved
Reserved
FWDTEN
Bit 15
IESO
IESO
Bit 7
—
(1)
(2)
(3)
FCKSM<1:0>
PWMLOCK
Reserved
Bit 14
PWMLOCK
(3)
WINDIS
HPOL
(2)
Bit 6
—
—
Table
PWMPIN
(1)
Bit 13
Table
GCP
(1)
23-2.
(2)
23-1.
GWRP
Bit 12
Reserved
WDTWIN<1:0>
IOL1WAY
PLLKEN
LPOL
Bit 5
—
—
(1)
Reserved
(3)
Bit 11
(4)
HPOL
Bit 10
Reserved
WDTPRE
ALTI2C1
FNOSC<2:0>
Bit 4
—
—
(2)
Bit 9 Bit 8
WDTWIN<1:0>
(3)
ICS<1:0>
FWDTEN WINDIS
Bit 7
FCKSM<1:0>
Bit 3
—
—
—
—
Bit 6
OSCIOFNC IOL1WAY LPOL
OSCIOFNC
PLLKEN
Bit 5
Bit 2
—
—
—
WDTPOST<3:0>
WDTPRE
Bit 4
FNOSC<2:0>
Bit 1
GCP
Bit 3
—
(2)
POSCMD<1:0>
ALTI2C1
WDTPOST<3:0>
ICS<1:0>
Bit 2
POSCMD<1:0>
Bit 1
GWRP
Bit 0
—
Bit 0