DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 77

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.0
The Interrupt Controller reduces the numerous periph-
eral interrupt request signals to a single interrupt
request signal to the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 CPU. It has the following
features:
• Up to eight processor exceptions and software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
7.1
The Interrupt Vector Table (IVT) is shown in
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight non-maskable trap vectors, plus up to 118
sources of interrupt. In general, each interrupt source
has its own vector. Each interrupt vector contains a 24-
bit-wide address. The value programmed into each
interrupt vector location is the starting address of the
associated Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 will take priority over interrupts at any
other vector address.
dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/
102 devices implement up to 26 unique interrupts and
4 nonmaskable traps. These are summarized in
Table 7-1
© 2011 Microchip Technology Inc.
source
support
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
INTERRUPT CONTROLLER
Interrupt Vector Table
and
of the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 41. “Interrupts
(Part IV)” (DS70300) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Table
7-2.
family
Figure
7-1.
Preliminary
of
in
7.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in
AIVT
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a way to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications to facilitate evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The
dsPIC33FJ16MC101/102 device clears its registers in
response to a Reset, forcing the PC to zero. The digital
signal controller then begins program execution at
location 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note:
is
Reset Sequence
provided
ALTERNATE INTERRUPT VECTOR
TABLE
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
dsPIC33FJ16GP101/102
by
the
Figure
ALTIVT
7-1. Access to the
DS70652C-page 77
control
and
bit