DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 73

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 6-2:
TABLE 6-2:
© 2011 Microchip Technology Inc.
Symbol
T
T
V
T
V
T
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
PWRT
FSCM
POR
BOR
POR
BOR
Oscillator Clock
Device Status
1.
2.
3.
4.
5.
6.
SYSRST
POR extension time
BOR extension time
POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V
V
BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
delay T
PWRT Timer: The power-up timer continues to hold the processor in Reset for a specific period of time (T
delay T
T
Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
Section 8.0 “Oscillator Configuration”
When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO
instruction at the Reset address, which redirects program execution to the appropriate start-up routine.
The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay
T
FSCM
POR
BOR
POR
PWRT
FSCM
Fail-safe Clock
V
POR threshold
BOR threshold
Power-up time
Monitor Delay
DD
Parameter
threshold and the delay T
PWRT
elapsed.
BOR
has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles.
OSCILLATOR PARAMETERS
delay
1
has elapsed. The delay T
ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay
SYSTEM RESET TIMING
2
T
V
POR
100 μs maximum
900 μs maximum
POR
30 μs maximum
64 ms nominal
POR
1.8V nominal
2.5V nominal
has elapsed.
Value
BOR
for more information.
ensures the voltage regulator output becomes stable.
Preliminary
Vbor
V
BOR
T
PWRT
T
3
BOR
Reset
Time
Note:
T
OSCD
When the device exits the Reset condi-
tion (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly. The
user application must ensure that the
delay between the time power is first
applied, and the time SYSRST becomes
inactive, is long enough to get all
operating
specification.
T
OST
4
DD
crosses the V
T
parameters
LOCK
PWRT
BOR
Table
) after a BOR. The
threshold and the
DS70652C-page 73
5
DD
6
6-1. Refer to
Run
crosses the
T
FSCM
within