DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 224

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 22-1:
DS70652C-page 224
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-0
Note 1:
CTMUEN
R/W-0
U-0
—
2:
If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more
information, see
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitance measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
CTMUSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
Unimplemented: Read as ‘0’
U-0
U-0
—
—
CTMUCON1: CTMU CONTROL REGISTER 1
Section 10.4 “Peripheral Pin
W = Writable bit
‘1’ = Bit is set
CTMUSIDL
R/W-0
U-0
—
TGEN
R/W-0
U-0
—
(1)
Preliminary
(1)
Select”.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
EDGEN
R/W-0
U-0
—
EDGSEQEN
R/W-0
U-0
—
© 2011 Microchip Technology Inc.
x = Bit is unknown
IDISSEN
R/W-0
U-0
—
(2)
CTTRIG
R/W-0
U-0
—
bit 8
bit 0