DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 165

• Manufacturer Part Number: DSPIC33FJ16MC101T-I/SS
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101T-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 15-10: PxFLTBCON: FAULT B CONTROL REGISTER
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-8
bit 7
bit 6-3
bit 2
bit 1
bit 0
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Note 1: Comparator outputs are not internally connected to the PWM Fault control logic. If using the Comparator
FLTBM
R/W-0
U-0
—
2: On dsPIC33FJ16MC101 (20-pin) devices, only the FLTA1 pin is supported, but it requires an external
3: On dsPIC33FJ16MC102 (28-pin) devices, both the FLTA1 and FLTB1 pins are supported and do not
4:
5: During any reset event, FLTB1 is enabled by default and must be cleared as described in
modules for Fault generation, the user must externally connect the desired comparator output pin to the
dedicated FLTA1 or FLTB1 input pin.
pull-down resistor for correct functionality.
require an external pull-down resistor.
Registers”
“PWM
The PxFLTACON register is a write-protected register. Refer to
Unimplemented: Read as ‘0’
FBOVxH<3:1>:FBOVxL<3:1>: Fault Input B PWM Override Value bits
1 = The PWM output pin is driven active on an external Fault input event
0 = The PWM output pin is driven inactive on an external Fault input event
FLTBM: Fault B Mode bit
1 = The Fault B input pin functions in the Cycle-by-Cycle mode
0 = The Fault B input pin latches all control pins to the programmed states in PxFLTBCON<13:8>
Unimplemented: Read as ‘0’
FBEN3: Fault Input B Enable bit
1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input B
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input B
FBEN2: Fault Input B Enable bit
1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input B
0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input B
FBEN1: Fault Input B Enable bit
1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input B
0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input B
Faults”.
U-0
U-0
—
—
for more information on the unlock sequence.
‘1’ = Bit is set
W = Writable bit
FBOV3H
R/W-0
U-0
—
FBOV3L
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FBOV2H
R/W-0
U-0
—
(1,2,3,4,5)
FBOV2L
FBEN3
R/W-0
R/W-1
Section 15.3 “Write-protected
x = Bit is unknown
FBOV1H
FBEN2
R/W-0
R/W-1
DS70652C-page 165
Section 15.2
FBOV1L
FBEN1
R/W-0
R/W-1
bit 8
bit 0