DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet - Page 183

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DSPIC33FJ16MC101T-I/SS

Manufacturer Part Number
DSPIC33FJ16MC101T-I/SS
Description
16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ16MC101T-I/SS

Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
18.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available
dsPIC33FJ16MC101/102 device family. The UART is a
full-duplex
communicate with peripheral devices, such as
personal computers, LIN 2.0, and RS-232, and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA
FIGURE 18-1:
© 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
in
of the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “UART”
(DS70188) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
asynchronous
the
®
dsPIC33FJ16GP101/102
UART SIMPLIFIED BLOCK DIAGRAM
encoder and decoder.
Hardware Flow Control
Baud Rate Generator
system
UART Transmitter
UART Receiver
IrDA
family
that
®
and
can
Preliminary
of
in
The primary features of the UART module are:
• Full-Duplex, 8-bit or 9-bit Data Transmission
• Even, Odd, or No Parity Options (for 8-bit data)
• One or two stop bits
• Hardware flow control option with UxCTS and
• Fully integrated Baud Rate Generator with 16-bit
• Baud rates ranging from 0.4 Mbps to 6 bps at 16x
• Baud rates ranging from 1.6 Mbps to 24.4 bps at 4x
• 4-deep First-In First-Out (FIFO) Transmit Data
• 4-deep FIFO Receive Data buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA
• 16x baud clock output for IrDA
A simplified block diagram of the UART module is
shown in
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
through the UxTX and UxRX pins
UxRTS pins
prescaler
mode at 16 MIPS
mode at 16 MIPS
buffer
(9th bit = 1)
®
encoder and decoder logic
Figure
18-1. The UART module consists of
UxRTS/BCLK
UxCTS
UxRX
UxTX
®
support
DS70652C-page 183

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