14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P

PIC16F1829-E/P

Manufacturer Part NumberPIC16F1829-E/P
Description14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
ManufacturerMicrochip Technology
SeriesPIC® XLP™ mTouch™ 16F
PIC16F1829-E/P datasheet
 

Specifications of PIC16F1829-E/P

Core ProcessorPICCore Size8-Bit
Speed32MHzConnectivityI²C, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o17
Program Memory Size14KB (8K x 14)Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 12x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 125°C
Package / Case*Processor SeriesPIC16F182x
CorePICData Bus Width8 bit
Data Ram Size1 KBInterface TypeI2C, SPI, USART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os18
Number Of Timers5Operating Supply Voltage1.8 V to 5.5 V
Maximum Operating Temperature+ 125 CMounting StyleThrough Hole
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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PIC16F/LF1825/1829
Data Sheet
14/20-Pin Flash Microcontrollers
with nanoWatt XLP Technology
Preliminary
 2010 Microchip Technology Inc.
DS41440A

PIC16F1829-E/P Summary of contents

  • Page 1

    ... Flash Microcontrollers  2010 Microchip Technology Inc. PIC16F/LF1825/1829 with nanoWatt XLP Technology Preliminary Data Sheet DS41440A ...

  • Page 2

    ... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 3

    ... Enhanced Low-Voltage Programming (LVP) • Operating Voltage Range: - 1.8V-5.5V (PIC16F1825/1829) - 1.8V-3.6V (PIC16LF1825/1829) • Programmable Code Protection • Power-Saving Sleep mode  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Extreme Low-Power Management PIC16LF1825/1829 with nanoWatt XLP: • Sleep mode • Watchdog Timer: 500 nA • ...

  • Page 4

    ... PIC16F/LF1825/1829 PIC16F/LF1825/1829 Family Types Program Data Memory Memory PIC16LF1825 8K 1024 PIC16F1825 8K 1024 PIC16LF1829 8K 1024 PIC16F1829 8K 1024 Note 1: One pin is input only. DS41440A-page 4 256 4/1 256 4/1 256 4/1 256 4/1 Preliminary Yes Yes Yes Yes  2010 Microchip Technology Inc. ...

  • Page 5

    FIGURE 1: 14-PIN DIAGRAM FOR PIC16F/LF1825 PDIP, SOIC, TSSOP (1) (1) CCP2 /P2A /T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) (1) T1G /P2B /SDO /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MCLR/V (1) MDCIN2/DT (1) (1) MDOUT/CK /TX /P1B/SRNQ/C2OUT/RC4 (1) (1) (1) (1) MDMIN/SS1 /P1C /CCP2 /P2A /C12IN3-/CPS7/AN7/RC3 Note 1: ...

  • Page 6

    FIGURE 2: 16-PIN DIAGRAM FOR PIC16F/LF1825 QFN (1) (1) CCP2 /P2A /T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) (1) T1G /P2B /SDO /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MCLR/V /T1G PP (1) (1) MDCIN2/DT /RX /CCP1/P1A/RC5 Note 1: Pin function is selectable via the APFCON0 or APFCON1 register. RA0/AN0/CPS0/C1IN+/V ...

  • Page 7

    ... RC5 5 4 — — — — — — — — — SS Note 1: Pin function is selectable via the APFCON0 or APFCON1 register.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 (1) C1IN+ — — — TX (1) CK (1) C12IN0- SRI — — RX (1) DT C1OUT SRQ T0CKI CCP3 — ...

  • Page 8

    FIGURE 3: 20-PIN DIAGRAM FOR PIC16F/LF1829 PDIP, SOIC, TSSOP (1) (1) (1) CCP2 /P2A /T1CKI/SD02 /T1OSI/OSC1/CLKIN/RA5 (1) (1) (1) T1G /P2B /SS2 /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MDCIN2/DT (1) (1) MDOUT/CK /TX (1) (1) (1) MDMIN/P2A /CCP2 /P1C /C12IN3-/CPS7/AN7/RC3 SS1/CCP4/CPS8/AN8/RC6 SCK2/SCL2/CK Note 1: Pin ...

  • Page 9

    FIGURE 4: PIC16F/LF1829 20-PIN QFN QFN 4x4 MDCIN2/DT (1) MDOUT/CK /TX (1) (1) MDMIN/P2A /CCP2 /P1C Note 1: Pin function is selectable via the APFCON0 or APFCON1 register. (1) 15 RA1/AN1/CPS1/C12IN0-/V MCLR/V /T1G /RA3 PP 1 (1) (1) 14 /RX ...

  • Page 10

    ... SDO2 — — Y — — — MDCIN1 Y — — — MDMIN Y — — — MDOUT Y — — — MDCIN2 Y — — — Y — SS1 SDO — — Y — — — — — — — — —  2010 Microchip Technology Inc. ...

  • Page 11

    ... Appendix B: Migrating From Other PIC® Devices ............................................................................................................................ 409 The Microchip Web Site .................................................................................................................................................................... 419 Customer Change Notification Service ............................................................................................................................................. 419 Customer Support ............................................................................................................................................................................. 419 Reader Response ............................................................................................................................................................................. 420 Product Identification System ........................................................................................................................................................... 421 Worldwide Sales and Service ........................................................................................................................................................... 422  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Preliminary DS41440A-page 11 ...

  • Page 12

    ... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41440A-page 12 to receive the most current information on all of our products. Preliminary  2010 Microchip Technology Inc. ...

  • Page 13

    ... Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 CCP4 Comparators C1 C2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6  2010 Microchip Technology Inc. PIC16F/LF1825/1829 of the and 1-3 show ● ● ● ● ● ● ● ● ● ● ● ...

  • Page 14

    ... See applicable chapters for more information on peripherals. 2: See Table 1-1 for peripherals available on specific devices. 3: PIC16F/LF1829 only. DS41440A-page 14 Program Flash Memory CPU (Figure 2-1) Timer1 Timer2 Timer4 Timer6 MSSP CCP4 ECCP2 CCP3 Preliminary EEPROM RAM PORTA (3) PORTB PORTC Comparators EUSART  2010 Microchip Technology Inc. ...

  • Page 15

    ... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Input Output Type Type TTL CMOS General purpose I/O ...

  • Page 16

    ... Comparator negative input. — CMOS PWM output. — CMOS PWM output. — CMOS SPI data output. ST — Modulator Carrier Input 1. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels  2010 Microchip Technology Inc. ...

  • Page 17

    ... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Input Output Type Type TTL CMOS General purpose I/O ...

  • Page 18

    ... Timer1 oscillator connection. — CMOS Clock Reference output. ST — Slave Select input 2. — CMOS PWM output. ST — Timer1 Gate input. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels  2010 Microchip Technology Inc. ...

  • Page 19

    ... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Input Output Type Type TTL CMOS General purpose I/O ...

  • Page 20

    ... A/D Channel 9 input. AN — Capacitive sensing input 9. — CMOS SPI data output. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels  2010 Microchip Technology Inc. ...

  • Page 21

    ... Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” details.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Saving”, for more for more Preliminary DS41440A-page 21 ...

  • Page 22

    ... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX  2010 Microchip Technology Inc. ...

  • Page 23

    ... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16F/LF1825/1829  2010 Microchip Technology Inc. PIC16F/LF1825/1829 The following features are associated with access and control of program memory and data memory: memory in • PCL and PCLATH • ...

  • Page 24

    ... BRW instruction is not available so the older table read 2000h method must be used. 7FFFh Preliminary Example 3-1. RETLW INSTRUCTION ;Add Index ;program counter to ;select data ;Index0 data ;Index1 data DATA_INDEX  2010 Microchip Technology Inc. ...

  • Page 25

    ... File Select Registers (FSR). See Section 3.5 Addressing” for more information.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC16F/LF1825/1829. These registers are listed below: • ...

  • Page 26

    ... Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. R-1/q R-1/q R/W-0 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) Preliminary Section 29.0 Summary”). R/W-0/u R/W-0/u (1) ( bit 0  2010 Microchip Technology Inc. ...

  • Page 27

    ... General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh  2010 Microchip Technology Inc. PIC16F/LF1825/1829 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC16F/LF1825/1829 Section 3 ...

  • Page 28

    TABLE 3-3: PIC16F/LF1825/1829 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...

  • Page 29

    TABLE 3-4: PIC16F/LF1825/1829 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 480h INDF0 500h 400h 401h INDF1 481h INDF1 501h 402h PCL 482h PCL 502h 403h STATUS 483h STATUS 503h 404h FSR0L 484h FSR0L 504h 405h FSR0H 485h FSR0H ...

  • Page 30

    TABLE 3-5: PIC16F/LF1825/1829 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...

  • Page 31

    TABLE 3-6: PIC16F/LF1825/1829 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...

  • Page 32

    ... FEDh STKPTR FEEh TOSL FEFh TOSH Legend: = Unimplemented data memory locations, read as ‘0’. DS41440A-page 32 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register summary for the device family are as follows: Device PIC16F/LF1825/1829 Preliminary  2010 Microchip Technology Inc. Bank(s) Page No ...

  • Page 33

    ... CPSCON1 — — Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1829 only. 3: PIC16F/LF1825 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

  • Page 34

    ... LFIOFR HFIOFS 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF<1:0> 0000 -000 0000 -000 —  2010 Microchip Technology Inc. Value on all other Resets — — — ...

  • Page 35

    ... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1829 only. 3: PIC16F/LF1825 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 — — BSR<4:0> ...

  • Page 36

    ... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00  2010 Microchip Technology Inc. ...

  • Page 37

    ... ACKTIM PCIE Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1829 only. 3: PIC16F/LF1825 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 — — BSR<4:0> ...

  • Page 38

    ... CCP2M1 CCP2M0 0000 0000 0000 0000 P2DC1 P2DC0 0000 0000 0000 0000 PSS2BD1 PSS2BD0 0000 0000 0000 0000 STR2B STR2A ---0 0001 ---0 0001 C1TSEL1 C1TSEL0 0000 0000 0000 0000 — —  2010 Microchip Technology Inc. ...

  • Page 39

    ... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1829 only. 3: PIC16F/LF1825 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

  • Page 40

    ... CLKRDIV<2:0> 0011 0000 0011 0000 — — — MDBIT 0010 ---0 0010 ---0 MDMS<3:0> x--- xxxx u--- uuuu MDCL<3:0> xxx- xxxx uuu- uuuu MDCH<3:0> xxx- xxxx uuu- uuuu  2010 Microchip Technology Inc. Value on all other Resets — — — — — — ...

  • Page 41

    ... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1829 only. 3: PIC16F/LF1825 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

  • Page 42

    ... INTF IOCIF 0000 000x 0000 000u — —  2010 Microchip Technology Inc. ...

  • Page 43

    ... Top-of-Stack High byte TOSH Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1829 only. 3: PIC16F/LF1825 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

  • Page 44

    ... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary  2010 Microchip Technology Inc. ...

  • Page 45

    ... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL  2010 Microchip Technology Inc. PIC16F/LF1825/1829 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...

  • Page 46

    ... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary  2010 Microchip Technology Inc. ...

  • Page 47

    ... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2010 Microchip Technology Inc. PIC16F/LF1825/1829 0x0F Return Address 0x0E Return Address ...

  • Page 48

    ... Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41440A-page 48 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary  2010 Microchip Technology Inc. ...

  • Page 49

    ... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 6 From Opcode 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Indirect Addressing 0 7 FSRxH Bank Select 11111 Bank 31 Preliminary ...

  • Page 50

    ... FIGURE 3-11: 7 FSRnH 1 0 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF  2010 Microchip Technology Inc. ...

  • Page 51

    ... Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 by device Preliminary DS41440A-page 51 ...

  • Page 52

    ... R/P-1/1 R/P-1/1 R/P-1/1 WDTE1 WDTE0 FOSC2 U = Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) Pin Function Select bit (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0  2010 Microchip Technology Inc. ...

  • Page 53

    ... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Preliminary DS41440A-page 53 ...

  • Page 54

    ... R/P-1/1 R/P-1/1 — BORV STVREN R-1 U-1 U-1 — — Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0  2010 Microchip Technology Inc. ...

  • Page 55

    ... See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification” (DS41390).  2010 Microchip Technology Inc. PIC16F/LF1825/1829 “Write such as Preliminary DS41440A-page 55 ...

  • Page 56

    ... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100111011 = PIC16F1825 100111111 = PIC16F1829 101000011 = PIC16LF1825 101000111 = PIC16LF1829 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. ...

  • Page 57

    ... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources  2010 Microchip Technology Inc. PIC16F/LF1825/1829 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...

  • Page 58

    ... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules  2010 Microchip Technology Inc. ...

  • Page 59

    ... Configuration Word 1: • High-power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low-power, 0-0.5 MHz (FOSC = 101)  2010 Microchip Technology Inc. PIC16F/LF1825/1829 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

  • Page 60

    ... Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic P (3) R (2) R Sleep F OSC2/CLKOUT S ( may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 4X PLL Specifications in Section 30.0  2010 Microchip Technology Inc. ) ...

  • Page 61

    ... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)  2010 Microchip Technology Inc. PIC16F/LF1825/1829 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...

  • Page 62

    ... OSCSTAT register indicates when the MFINTOSC is running and can be utilized. Preliminary (Register 5-3). Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. Internal Oscillator Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information.  2010 Microchip Technology Inc. ...

  • Page 63

    ... Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...

  • Page 64

    ... Clock switching time delays are shown in Start-up delay specifications are located in the oscillator tables of Specifications” Preliminary  2010 Microchip Technology Inc. Figure 5-7). If this is the Table 5-1. Section 30.0 “Electrical ...

  • Page 65

    ... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Start-up Time 2-cycle Sync 0 2-cycle Sync  LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync  ...

  • Page 66

    ... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Start-up or Preliminary Section 21.0 for more  2010 Microchip Technology Inc. ...

  • Page 67

    ... Any clock source LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active Note 1: PLL inactive.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...

  • Page 68

    ... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary  2010 Microchip Technology Inc. ...

  • Page 69

    ... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...

  • Page 70

    ... Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS41440A-page 70 Oscillator Failure Test Test Preliminary Failure Detected Test  2010 Microchip Technology Inc. ...

  • Page 71

    ... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Note 1: Duplicate frequency derived from HFINTOSC.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Section 5 ...

  • Page 72

    ... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41440A-page 72 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0  2010 Microchip Technology Inc. ...

  • Page 73

    ... CP MCLRE Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16F1825/1829 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

  • Page 74

    ... PIC16F/LF1825/1829 NOTES: DS41440A-page 74 Preliminary  2010 Microchip Technology Inc. ...

  • Page 75

    ... Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 6.3 Conflicts with the CLKR Pin ...

  • Page 76

    ... R/W-0/0 CLKRDC1 CLKRDC0 CLKRDIV2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. See Section 6.3 “Conflicts with the CLKR Pin” Preliminary R/W-0/0 R/W-0/0 CLKRDIV1 CLKRDIV0 bit 0 for details.  2010 Microchip Technology Inc. ...

  • Page 77

    ... Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 ...

  • Page 78

    ... PIC16F/LF1825/1829 NOTES: DS41440A-page 78 Preliminary  2010 Microchip Technology Inc. ...

  • Page 79

    ... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable  2010 Microchip Technology Inc. PIC16F/LF1825/1829 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41440A-page 79 ...

  • Page 80

    ... V for a DD BOR , the device BORDC for more information. Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD  2010 Microchip Technology Inc. ...

  • Page 81

    ... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive  2010 Microchip Technology Inc. PIC16F/LF1825/1829 T BORRDY BOR Protection Active (1) T PWRT < T ...

  • Page 82

    ... Upon bringing MCLR high, the device will begin execution immediately (see is useful for testing purposes or to synchronize more than one device operating in parallel. Section 10.0 Table 7-4 for Preliminary Timer configuration. See for more information. Figure 7-4). This  2010 Microchip Technology Inc. ...

  • Page 83

    ... FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC  2010 Microchip Technology Inc. PIC16F/LF1825/1829 T PWRT T MCLR T OST Preliminary DS41440A-page 83 ...

  • Page 84

    ... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu  2010 Microchip Technology Inc. ...

  • Page 85

    ... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2010 Microchip Technology Inc. PIC16F/LF1825/1829 7-2. U-0 R/W/HC-1/q R/W/HC-1/q — ...

  • Page 86

    ... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS41440A-page 86 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Preliminary Register Bit 1 Bit 0 on Page — BORRDY 81 POR BOR 107  2010 Microchip Technology Inc. ...

  • Page 87

    ... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2)  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE Preliminary Interrupt to CPU DS41440A-page 87 ...

  • Page 88

    ... ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE CCP5IF CCP5IE TMR1IF TMR1IE TMR6IF TMR6IE EEIF EEIE OSFIF OSFIE C1IF C1IE C2IF C2IE BCL1IF BCL1IE (1) BCL2IF (1) BCL2IE Note 1: PIC16F/LF1829 only. DS41440A-page 88 Preliminary  2010 Microchip Technology Inc. To Interrupt Logic (Figure 8-1) ...

  • Page 89

    ... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...

  • Page 90

    ... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h)  2010 Microchip Technology Inc. ...

  • Page 91

    ... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Q2 Q3 ...

  • Page 92

    ... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41440A-page 92 Preliminary  2010 Microchip Technology Inc. ...

  • Page 93

    ... None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCxF register have been cleared by software.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Note: Interrupt flag bits are set when an interrupt ...

  • Page 94

    ... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0  2010 Microchip Technology Inc. ...

  • Page 95

    ... Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 Interrupt 0 = Disables the CCP2 Interrupt Note 1: PIC16F/LF1829 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...

  • Page 96

    ... Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IE — bit 0  2010 Microchip Technology Inc. ...

  • Page 97

    ... SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt Note 1: This register is only available on PIC16F/LF1829.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Note 1: The PIE4 register is available only on the PIC16F/LF1829 device. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt ...

  • Page 98

    ... R-0/0 R/W-0/0 R/W-0/0 TXIF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary  2010 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...

  • Page 99

    ... Interrupt is pending 0 = Interrupt is not pending bit 0 Unimplemented: Read as ‘0’ Note 1: PIC16F/LF1829 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. ...

  • Page 100

    ... R/W-0/0 R/W-0/0 U-0 CCP3IF TMR6IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IF — bit 0  2010 Microchip Technology Inc. ...

  • Page 101

    ... SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit 1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software Waiting to Transmit/Receive/Bus Condition in progress Note 1: This register is only available on PIC16F/LF1829.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Note 1: The PIR4 register is available only on the PIC16F/LF1829 device. 2: Interrupt flag bits are set when an inter- ...

  • Page 102

    ... CCP3IF TMR6IF — — — — — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 93 PS1 PS0 189 TMR2IE TMR1IE 94 — CCP2IE 95 TMR4IE — 96 BCL2IE SSP2IE 97 TMR2IF TMR1IF 98 — CCP2IF 99 TMR4IF — 100 BCL2IF SSP2IF 101  2010 Microchip Technology Inc. ...

  • Page 103

    ... Converter (DAC) Module” and Section 14.0 “Fixed Voltage Reference (FVR)” for more information on these modules.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

  • Page 104

    ... INTF IOCIF 93 IOCAF1 IOCAF0 144 IOCAN1 IOCAN0 144 IOCAP1 IOCAP0 144 — — 146 — — 145 — — 145 TMR2IE TMR1IE 94 — CCP2IE 95 BCL2IE SSP2IE 97 TMR2IF TMR1IF 98 — CCP2IF 99 BCL2IF SSP2IF 101 WDTPS0 SWDTEN 107  2010 Microchip Technology Inc. ...

  • Page 105

    ... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep  2010 Microchip Technology Inc. PIC16F/LF1825/1829 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41440A-page 105 ...

  • Page 106

    ... STATUS register are changed to indicate the Active event. See Section 3.0 “Memory Organization” Active more information. Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more for WDT Cleared Cleared until the end of OST Unaffected  2010 Microchip Technology Inc. ...

  • Page 107

    ... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...

  • Page 108

    ... PIC16F/LF1825/1829 NOTES: DS41440A-page 108 Preliminary  2010 Microchip Technology Inc. ...

  • Page 109

    ... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...

  • Page 110

    ... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary  2010 Microchip Technology Inc. (Register 5-1) ...

  • Page 111

    ... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT  2010 Microchip Technology Inc. PIC16F/LF1825/1829 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...

  • Page 112

    ... NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Boundary 32 words, = 00000 Preliminary instruction on the next  2010 Microchip Technology Inc. ...

  • Page 113

    ... NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2010 Microchip Technology Inc. PIC16F/LF1825/1829 (Figure 11-1) (Figure 11-1) Preliminary DS41440A-page 113 ...

  • Page 114

    ... However, the entire write latch block will be written to program memory. An example of the complete write sequence for eight words is shown in Example loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. Preliminary  2010 Microchip Technology Inc. 11-5. The initial address is ...

  • Page 115

    ... EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 Buffer Register  2010 Microchip Technology Inc. PIC16F/LF1825/1829 continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...

  • Page 116

    ... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary  2010 Microchip Technology Inc. ...

  • Page 117

    ... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE  2010 Microchip Technology Inc. PIC16F/LF1825/1829 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...

  • Page 118

    ... Table When read access is initiated on an address outside the parameters listed in register pair is cleared. Function Read Access User IDs Yes Yes Yes Figure 11-1) Figure 11-1) Preliminary 11-2. Table 11-2, the EEDATH:EEDATL Write Access Yes No No  2010 Microchip Technology Inc. ...

  • Page 119

    ... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Preliminary DS41440A-page 119 ...

  • Page 120

    ... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0  2010 Microchip Technology Inc. ...

  • Page 121

    ... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W/HC-0/0 R/W-x/q R/W-0/0 ...

  • Page 122

    ... WREN EEADRL<7:0> EEADRH<6:0 EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCL1IE — EEIF BCL1IF — Preliminary W-0/0 W-0/0 bit 0 Register Bit 1 Bit 0 on Page WR RD 121 122* 120 120 120 120 INTF IOCIF 93 — CCP2IE 95 — CCP2IF 99  2010 Microchip Technology Inc. ...

  • Page 123

    ... Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 FIGURE 12-1: D Write LATx Write PORTx ...

  • Page 124

    ... SS (Slave Select) • T1G • P1B/P1C/P1D/P2B • CCP1/P1A/CCP2 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. DS41440A-page 124 and Preliminary  2010 Microchip Technology Inc. ...

  • Page 125

    ... TX/CK function is on RA0 For 20 Pin Devices (PIC16F/LF1829 TX/CK function is on RB7 1 = TX/CK function is on RC4 bit 1-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC16F/LF1825/1829 U-0 R/W-0/0 R/W-0/0 T1GSEL TXCKSEL — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

  • Page 126

    ... CCP2 function is on RA5 Note 1: PIC16F/LF1829 only. DS41440A-page 126 R/W-0/0 R/W-0/0 R/W-0/0 (1) (1) SS2SEL P1DSEL P1CSEL U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (1) Preliminary R/W-0/0 R/W-0/0 P2BSEL CCP2SEL bit 0  2010 Microchip Technology Inc. ...

  • Page 127

    ... Changing the threshold level during the time a module is active may inadvertently generate a tran- sition associated with an input pin, regard- less of the actual voltage level on that pin.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 12.2.1 ANSELA REGISTER The ANSELA register configure the Input mode of an I/O pin to analog ...

  • Page 128

    ... DS41440A-page 128 RA0 1. ICSPDAT 2. ICDDAT 3. DACOUT (DAC) RA1 1. ICSPCLK 2. ICDCLK 3. RX/DT (EUSART) RA2 1. SRQ 2. C1OUT (Comparator) 3. CCP3 RA3 No output priorities. Input only pin. RA4 1. CLKOUT 2. T1OSO 3. CLKR 4. SDO 5. P2B RA5 1. SDO2 (MSSP) (PIC16F/LF1829 only) 2. CCP2/P2A Preliminary  2010 Microchip Technology Inc. ...

  • Page 129

    ... TRISA3: RA3 Port Tri-State Control bit This bit is always ‘1’ as RA3 is an input only bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated PORTA pin configured as an output  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-x/x R-x/x R/W-x/x RA4 ...

  • Page 130

    ... R/W-1/1 ANSA4 — ANSA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. (1) . Digital input buffer disabled. Preliminary R/W-x/u R/W-x/u LATA1 LATA0 bit 0 R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0  2010 Microchip Technology Inc. ...

  • Page 131

    ... Unimplemented: Read as ‘0’ bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits For RA<5:0> pins, respectively input used for port reads and interrupt-on-change 0 = TTL input used for port reads and interrupt-on-change  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-1/1 R/W-1/1 R/W-1/1 WPUA4 ...

  • Page 132

    ... ANSA1 ANSA0 130 — — 125 P2BSEL CCP2SEL 126 INLVLA1 INLVLA0 131 LATA1 LATA0 130 PS<2:0> 189 RA2 RA1 RA0 129 TRISA1 TRISA0 129 WPUA1 WPUA0 131 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> CPD 52 FOSC<2:0>  2010 Microchip Technology Inc. ...

  • Page 133

    ... Changing the threshold level during the time a module is active may inadvertently generate a tran- sition associated with an input pin, regard- less of the actual voltage level on that pin.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 12.3.1 ANSELB REGISTER The ANSELB register configure the Input mode of an I/O pin to analog ...

  • Page 134

    ... These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. RB4 1. SDA (MSSP) RB5 1. SDA2 (MSSP) (PIC16F1829 only) 2. RX/DT (EUSART) RB6 1. SCL/SCK (MSSP) RB7 1. TX/CK (EUSART) ...

  • Page 135

    ... LATB<7:4>: PORTB Output Latch Value bits bit 3-0 Unimplemented: Read as ‘0’ Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-x/u U-0 U-0 RB4 — ...

  • Page 136

    ... R/W-0/0 U-0 U-0 INLVLB4 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ’ Preliminary U-0 U-0 — — bit 0 U-0 U-0 — — bit 0 U-0 U-0 — — bit 0  2010 Microchip Technology Inc. ...

  • Page 137

    ... RB6 TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. Note 1: PIC16F/LF1829 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 — — INLVLB5 INLVLB4 — ...

  • Page 138

    ... CLRF PORTC BANKSEL LATC CLRF LATC BANKSEL ANSELC CLRF ANSELC BANKSEL TRISC MOVLW B’00110000’;Set RC<5:4> as inputs MOVWF TRISC Preliminary (Register 12-12) is used to INITIALIZING PORTC ; ;Init PORTC ;Data Latch ; ;Make RC<5:0> digital ; ;and RC<3:0> as outputs ;  2010 Microchip Technology Inc. ...

  • Page 139

    ... These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 RC0 1. SCL (MSSP) (PIC16F/LF1825 only) 2 ...

  • Page 140

    ... R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1, 2) Preliminary R/W-x/u R/W-x/u RC1 RC0 bit 0 R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 R/W-x/u R/W-x/u LATC1 LATC0 bit 0  2010 Microchip Technology Inc. ...

  • Page 141

    ... Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. 3: WPUC<7:6> available on PIC16F/LF1829 only. Otherwise, they are unimplemented and read as ‘0’.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 U-0 R/W-1/1 R/W-1/1 — ...

  • Page 142

    ... TRISC4 TRISC3 TRISC2 WPUC5 WPUC4 WPUC3 WPUC2 Preliminary R/W-0/0 R/W-0/0 INLVLC1 INLVLC0 bit 0 Register Bit 1 Bit 0 on Page ANSC1 ANSC0 136 INLVLC1 INLVLC0 142 LATC1 LATC0 135 RC1 RC0 135 TRISC1 TRISC0 135 WPUC1 WPUC0 136  2010 Microchip Technology Inc. ...

  • Page 143

    ... CK R RAx IOCAPx  2010 Microchip Technology Inc. PIC16F/LF1825/1829 13.3 Interrupt Flags The IOCAFx and IOCBFx bits located in the IOCAF and IOCBF registers, respectively, are status flags that correspond to the Interrupt-on-change pins of the associated port expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...

  • Page 144

    ... R/W/HS-0/0 IOCAF4 IOCAF3 IOCAF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCAP1 IOCAP0 bit 0 R/W-0/0 R/W-0/0 IOCAN1 IOCAN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCAF1 IOCAF0 bit 0  2010 Microchip Technology Inc. ...

  • Page 145

    ... Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge Interrupt-on-Change disabled for the associated pin. bit 5-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-0/0 U-0 U-0 IOCBP4 — ...

  • Page 146

    ... INLVLA1 INLVLA0 131 136 — — INTF IOCIF 93 IOCAF1 IOCAF0 144 IOCAN1 IOCAN0 144 IOCAP1 IOCAP0 144 — — 146 — — 145 — — 145 TRISA1 TRISA0 129 — — 135  2010 Microchip Technology Inc. ...

  • Page 147

    ... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY  2010 Microchip Technology Inc. PIC16F/LF1825/1829 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each , with 1 ...

  • Page 148

    ... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (High Range) (Low Range Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 Preliminary R/W-0/0 R/W-0/0 ADFVR1 ADFVR0 bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 148  2010 Microchip Technology Inc. ...

  • Page 149

    ... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 FIGURE 15-1: 15.2 Minimum Operating V ...

  • Page 150

    ... PIC16F/LF1825/1829 NOTES: DS41440A-page 150 Preliminary  2010 Microchip Technology Inc. ...

  • Page 151

    ... DAC FVR Buffer1 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: PIC16F/LF1829 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADNREF = 1 ...

  • Page 152

    ... The ADNREF bits of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: • pin REF • DS41440A-page 152 See Section 14.0 “Fixed Voltage Reference (FVR)” for more details on the fixed voltage reference. Refer to Section 16.2 Preliminary  2010 Microchip Technology Inc. ...

  • Page 153

    ... ADC clock selections. Note: Unless using the F , any changes in the RC system clock frequency will change the ADC clock frequency, adversely affect the ADC result.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 peri- AD specifica- AD for which may Preliminary DS41440A-page 153 ...

  • Page 154

    ...  2010 Microchip Technology Inc. ...

  • Page 155

    ... MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC16F/LF1825/1829 16.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. ...

  • Page 156

    ... Using the Special Event Trigger does not assure proper ADC timing the user’s responsibility to ensure that the ADC timing requirements are met. Refer to Section 24.0 “Capture/Compare/PWM Mod- ules” for more information. Preliminary  2010 Microchip Technology Inc. RC CCPx/ECCPx CCP4 ...

  • Page 157

    ... Sleep and resume in-line code execution. 2: Refer to Section 16.3 “A/D Acquisition Requirements”.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 EXAMPLE 16-1: ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ...

  • Page 158

    ... DS41440A-page 158 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (4) (3) Module”for more information. for more information. for more information. Preliminary R/W-0/0 R/W-0/0 GO/DONE ADON bit 0  2010 Microchip Technology Inc. ...

  • Page 159

    ... V REF connected to internal Fixed Voltage Reference (FVR) module REF Note 1: When selecting the FVR or the V minimum voltage specification exists. See  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-0/0 U-0 R/W-0/0 — ADNREF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

  • Page 160

    ... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u — — bit 0  2010 Microchip Technology Inc. ...

  • Page 161

    ... W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-x/u R/W-x/u R/W-x/u — — — Unimplemented bit, read as ‘0’ ...

  • Page 162

    ... HOLD Preliminary Equation 16-1 may be 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED  2010 Microchip Technology Inc. ...

  • Page 163

    ... Resistance of Sampling Switch Sampling Switch V = Threshold Voltage T Note 1: Refer to Section 30.0 “Electrical FIGURE 16-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 03h 02h 01h 00h V - REF  2010 Microchip Technology Inc. PIC16F/LF1825/1829 V DD Sampling Switch  0.  Rss R IC LEAKAGE (1) I  0. ...

  • Page 164

    ... CCP4M1 CCP4M0 240 INLVLA1 INLVLA0 131 — — 136 INLVLC1 INLVLC0 142 INTF IOCIF 93 TMR2IE TMR1IE 94 TMR2IF TMR1IF 98 TRISA1 TRISA0 129 — — 135 TRISC1 TRISC0 140 ADFVR1 ADFVR0 148 — DACNSS 168 DACR1 DACR0 168  2010 Microchip Technology Inc. ...

  • Page 165

    ... Section 30.0 Specifications”.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 17.3 DAC Voltage Reference Output The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to ‘1’. Selecting the DAC reference voltage for output on the ...

  • Page 166

    ... VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41440A-page 166 Digital-to-Analog Converter (DAC SRC Steps SRC + DACOUT – Preliminary DACR<4:0> 5 DAC (To Comparator, CPS and ADC Modules) DACOUT DACOE Buffered DAC Output  2010 Microchip Technology Inc. ...

  • Page 167

    ... DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 This is also the method used to output the voltage level from the FVR to an output pin. See “ ...

  • Page 168

    ... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 DACR<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets 5 -))*(DACR<4:0>/( SRC Preliminary U-0 R/W-0/0 — DACNSS bit 0 R/W-0/0 R/W-0/0 bit 0  2010 Microchip Technology Inc. ...

  • Page 169

    ... Bit 7 Bit 6 FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 DACOE — DACPSS1 DACPSS0 — ...

  • Page 170

    ... PIC16F/LF1825/1829 NOTES: DS41440A-page 170 Preliminary  2010 Microchip Technology Inc. ...

  • Page 171

    ... Note: Enabling both the Set and Reset inputs from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...

  • Page 172

    ... SYNCC2OUT (4) SRRC2E (3) SYNCC1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. 4: PIC16F/LF1829 only. DS41440A-page 172 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary  2010 Microchip Technology Inc. SRQ SRNQ ...

  • Page 173

    ... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse Reset input for 1 Q-clock period effect on Reset input. Note 1: Set only, always reads back ‘0’.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 MHz MHz OSC OSC 39 ...

  • Page 174

    ... C1 Comparator output has no effect on the Reset input of the SR Latch Note 1: PIC16F/LF1829 only. DS41440A-page 174 R/W-0/0 R/W-0/0 R/W-0/0 (1) SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (1) Preliminary R/W-0/0 R/W-0/0 (1) SRRC2E SRRC1E bit 0  2010 Microchip Technology Inc. ...

  • Page 175

    ... SRSCKE TRISA — — (1) (1) TRISC TRISC7 TRISC6 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR Latch module. Note 1: PIC16F/LF1829 only.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 INLVLA5 INLVLA4 INLVLA3 ...

  • Page 176

    ... PIC16F/LF1825/1829 NOTES: DS41440A-page 176 Preliminary  2010 Microchip Technology Inc. ...

  • Page 177

    ... When CxON = 0, the Comparator will produce a ‘0’ at the output. 2: When CxON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 comparator is a digital low level. When the analog voltage the output of the comparator is a digital high level. ...

  • Page 178

    ... The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the CxSP bit to ‘0’. Preliminary COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS CxPOL CxOUT  2010 Microchip Technology Inc. ...

  • Page 179

    ... Block Diagram (Figure 19-2) and the Timer1 Block Diagram (Figure 21-1) for more information.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present ...

  • Page 180

    ... Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. Preliminary  2010 Microchip Technology Inc. and V . The DD SS and V . ...

  • Page 181

    ... Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 “Electrical  2010 Microchip Technology Inc. PIC16F/LF1825/1829 V DD  0. (1) I LEAKAGE  0. Vss Specifications”. Preliminary To Comparator DS41440A-page 181 ...

  • Page 182

    ... Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. DS41440A-page 182 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxHYS CxSYNC bit 0  2010 Microchip Technology Inc. ...

  • Page 183

    ... Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

  • Page 184

    ... MC2OUT MC1OUT 183 — DACNSS 168 DACR1 DACR0 168 ADFVR1 ADFVR0 148 INLVLA1 INLVLA0 131 INLVLC1 INLVLC0 142 INTF IOCIF 93 — CCP2IE 95 — CCP2IF 99 RC1 RC0 140 LATC1 LATC0 140 TRISA1 TRISA0 129 TRISC1 TRISC0 140  2010 Microchip Technology Inc. ...

  • Page 185

    ... From CPSCLK 1 TMR0SE TMR0CS T0XCS  2010 Microchip Technology Inc. PIC16F/LF1825/1829 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘ ...

  • Page 186

    ... Section 30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41440A-page 188 Preliminary  2010 Microchip Technology Inc. ...

  • Page 187

    ... Timer0 Module Register TRISA — — Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...

  • Page 188

    ... PIC16F/LF1825/1829 NOTES: DS41440A-page 190 Preliminary  2010 Microchip Technology Inc. ...

  • Page 189

    ... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...

  • Page 190

    ... T1CKI is low. T1OSCEN System Clock ( OSC Instruction Clock (F x OSC Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4)  2010 Microchip Technology Inc. ...

  • Page 191

    ... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...

  • Page 192

    ... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary Figure 21-6 for  2010 Microchip Technology Inc. ...

  • Page 193

    ... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 21.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...

  • Page 194

    ... PIC16F/LF1825/1829 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41440A-page 196 Preliminary  2010 Microchip Technology Inc ...

  • Page 195

    ... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41440A-page 197 ...

  • Page 196

    ... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41440A-page 198 Set by hardware on falling edge of T1GVAL Preliminary  2010 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...

  • Page 197

    ... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop  2010 Microchip Technology Inc. PIC16F/LF1825/1829 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...

  • Page 198

    ... Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) DS41440A-page 200 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0  2010 Microchip Technology Inc. ...

  • Page 199

    ... TRISA T1CON TMR1CS1 TMR1CS0 T1GCON TMR1GE T1GPOL Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information.  2010 Microchip Technology Inc. PIC16F/LF1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 DC1B1 ...

  • Page 200

    ... PIC16F/LF1825/1829 NOTES: DS41440A-page 202 Preliminary  2010 Microchip Technology Inc. ...