PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 76

• Manufacturer Part Number: PIC16F1829-E/P
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F1829-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16F182x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1825/1829
REGISTER 6-1:
DS41440A-page 76
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4-3
bit 2-0
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
CLKREN
R/W-0/0
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration
is selected.
Word 1 = 0 will result in F
CLKREN: Reference Clock Module Enable bit
1 = Reference Clock module is enabled
0 = Reference Clock module is disabled
CLKROE: Reference Clock Output Enable bit
1 = Reference Clock output is enabled on CLKR pin
0 = Reference Clock output disabled on CLKR pin
CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit
1 = Slew Rate limiting is enabled
0 = Slew Rate limiting is disabled
CLKRDC<1:0>: Reference Clock Duty Cycle bits
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
CLKRDIV<2:0> Reference Clock Divider bits
111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2
000 = Base clock value
CLKROE
R/W-0/0
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
CLKRSLR
R/W-1/1
OSC
(2)
/4. See
CLKRDC1
R/W-1/1
Section 6.3 “Conflicts with the CLKR Pin”
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
CLKRDC0
(3)
R/W-0/0
CLKRDIV2
R/W-0/0
 2010 Microchip Technology Inc.
CLKRDIV1
R/W-0/0
for details.
CLKRDIV0
R/W-0/0
bit 0