PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 154

• Manufacturer Part Number: PIC16F1829-E/P
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F1829-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16F182x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1825/1829
TABLE 16-1:
FIGURE 16-2:
DS41440A-page 154
Legend:
Note 1:
Clock Source
ADC Clock Period (T
Fosc/16
Fosc/32
Fosc/64
Fosc/2
Fosc/4
Fosc/8
ADC
F
2:
3:
4:
RC
T
CY
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
Shaded cells are outside of recommended range.
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
The ADC clock period (T
system clock F
device in Sleep mode.
- T
AD
Conversion starts
RC
ADCS<2:0>
ADC CLOCK PERIOD (T
T
AD
source has a typical T
000
100
001
101
010
110
x11
1 T
ANALOG-TO-DIGITAL CONVERSION T
AD
OSC
)
AD
b9
. However, the F
2 T
1.0-6.0 s
62.5ns
125 ns
0.5 s
AD
32 MHz
AD
b8
800 ns
1.0 s
2.0 s
3 T
) and total ADC conversion time can be minimized when the ADC clock is derived from the
(2)
(2)
(2)
AD
AD
(1,4)
b7
time of 1.6 s for V
4 T
RC
1.0-6.0 s
clock source must be used when conversions are to be performed with the
AD
AD
b6
100 ns
200 ns
400 ns
20 MHz
800 ns
1.6 s
3.2 s
5 T
) V
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Preliminary
AD
S
AD
(2)
(2)
(2)
b5
. DEVICE OPERATING FREQUENCIES
time.
(1,4)
6 T
DD
AD
b4
1.0-6.0 s
.
Device Frequency (F
7 T
125 ns
250 ns
0.5 s
16 MHz
1.0 s
2.0 s
4.0 s
AD
b3
(2)
(2)
(2)
AD
8
(1,4)
CYCLES
T
AD
b2
1.0-6.0 s
9 T
250 ns
500 ns
8.0 s
8 MHz
1.0 s
2.0 s
4.0 s
AD
b1
OSC
10
(3)
(2)
(2)
(1,4)
)
T
AD
b0
 2010 Microchip Technology Inc.
11
1.0-6.0 s
16.0 s
500 ns
8.0 s
4 MHz
1.0 s
2.0 s
4.0 s
(3)
(2)
(3)
(1,4)
1.0-6.0 s
16.0 s
32.0 s
64.0 s
8.0 s
1 MHz
2.0 s
4.0 s
(3)
(3)
(3)
(3)
(1,4)