PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 332

14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P

PIC16F1829-E/P

Manufacturer Part Number
PIC16F1829-E/P
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet

Specifications of PIC16F1829-E/P

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC16F182x
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC16F/LF1825/1829
REGISTER 27-2:
TABLE 27-3:
DS41440A-page 334
ANSELA
ANSELC
CPSCON0
CPSCON1
INLVLA
INLVLB
INLVLC
INTCON
OPTION_REG
T1CON
TRISA
TRISB
TRISC
Legend:
Note
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Note 1:
Name
(1)
U-0
(1)
1:
— = Unimplemented locations, read as ‘0’. Shaded cells are not used by the CPS module.
PIC16F/LF1829 only.
These channels are only implemented on the PIC16F/LF1829.
INLVLC7
TMR1CS1
TRISC7
ANSC7
Unimplemented: Read as ‘0’
CPSCH<3:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
If CPSON = 1:
INLVLB7
WPUEN
CPSON
TRISB7
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Bit 7
GIE
These bits are ignored. No channel is selected.
U-0
0000 = channel 0, (CPS0)
0001 = channel 1, (CPS1)
0010 = channel 2, (CPS2)
0011 = channel 3, (CPS3)
0100 = channel 4, (CPS4)
0101 = channel 5, (CPS5)
0110 = channel 6, (CPS6)
0111 = channel 7, (CPS7)
1000 = channel 8, (CPS4)
1001 = channel 9, (CPS5)
1010 = channel 10, (CPS6)
1011 = channel 11, (CPS7)
1100 = Reserved. Do not use.
1111 = Reserved. Do not use.
(1)
(1)
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
(1)
INLVLC6
TMR1CS0
TRISC6
ANSC6
INLVLB6
INTEDG
CPSRM
TRISB6
PEIE
Bit 6
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
(1)
(1)
(1)
U-0
T1CKPS1
TMR0CS
INLVLA5
INLVLB5
INLVLC5
TMR0IE
TRISC5
TRISA5
TRISB5
Bit 5
(1)
(1)
(1)
(1)
U-0
T1CKPS0
Preliminary
TMR0SE
INLVLA4
INLVLB4
INLVLC4
TRISC4
TRISA4
TRISB4
ANSA4
Bit 4
INTE
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
CPSRNG1
T1OSCEN
CPSCH3
INLVLA3
INLVLC3
TRISC3
TRISA3
ANSC3
IOCIE
Bit 3
PSA
CPSCH<3:2>
(1)
CPSRNG0
CPSCH2
INLVLA2
INLVLC2
T1SYNC
TMR0IF
TRISA2
TRISC2
ANSC2
ANSA2
Bit 2
PS2
R/W-0/0
CPSOUT
CPSCH1
INLVLA1
INLVLC1
TRISA1
TRISC1
ANSC1
ANSA1
Bit 1
INTF
PS1
 2010 Microchip Technology Inc.
R/W-0/0
TMR1ON
CPSCH0
INLVLC0
INLVLA0
CPSCH<1:0>
TRISA0
TRISC0
ANSC0
ANSA0
T0XCS
IOCIF
Bit 0
PS0
R/W-0/0
Register on
Page
130
141
333
334
131
136
142
189
199
129
135
140
93
bit 0

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