TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 

Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Table 13: Reset Specifications
#
Symbol
RP# Pulse Low Time
P1
t
PLPH
(If RP# is tied to V
RP# High to Reset during Block Erase, Program, or Lock-Bit
P2
t
PHRH
Configuration
P3
t
Vcc Power Valid to RP# de-assertion (high)
VCCPH
Notes:
1.
These specifications are valid for all product versions (packages and speeds).
2.
If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns.
3.
A reset time, t
, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are
PHQV
valid.
7.5
AC Test Conditions
Figure 17: AC Input/Output Reference Waveform
V
CCQ
Input V
/2
CCQ
0.0
Note:
AC test inputs are driven at V
CCQ
V
/2 V (50% of V
). Input rise and fall times (10% to 90%) < 5 ns.
CCQ
CCQ
Figure 18: Transient Equivalent Testing Load Circuit
Note:
C
Includes Jig Capacitance
L
Figure 19: Test Configuration
Test Configuration
V
= V
CCQ
CCQMIN
Datasheet
30
Numonyx™ Embedded Flash Memory (J3 v. D)
Parameter
, this specification is not applicable)
CC
Test Points
for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
Device
Under Test
Min
Max
Unit
Notes
25
µs
100
ns
60
µs
V
/2
Output
CCQ
Out
C
L
C
(pF)
L
30
November 2007
308551-05
1,2
1,3