TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory (J3 v. D)
7.0
AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention:
Figure 9:
Timing Signal Naming Convention
Source Signal
Source State
Figure 10: Timing Signal Name Decoder
Signal
Address
A
Data - Read
Q
Data - Write
D
Chip Enable (CE#)
E
Output Enable (OE#)
G
Write Enable (WE#)
W
Address Valid (ADV#)
V
Reset (RST#)
P
Clock (CLK)
C
WAIT
T
Note:
Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol
that refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and
tGLQV (whichever is satisfied last) of the flash device. tAPA is specified in the flash
device’s data sheet, and is the address-to-data delay for subsequent page-mode reads.
7.1
Read Specifications
Table 10: Read Operations (Sheet 1 of 2)
Asynchronous Specifications V
#
Sym
Parameter
R1
t
Read/Write Cycle Time
AVAV
November 2007
308551-05
t
E
L Q V
Target State
Target Signal
Code
State
High
Low
High-Z
Low-Z
Valid
Invalid
(3)
= 2.7 V–3.6 V
and V
CC
Density
Min
32 Mbit
75
64 Mbit
75
128 Mbit
75
256 Mbit
95
Code
H
L
Z
X
V
I
(3)
= 2.7 V–3.6 V
CCQ
Max
Unit
Notes
1,2
1,2
ns
1,2
1,2
Datasheet
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