TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory (J3 v. D)
Figure 11: Single Word Asynchronous Read Waveform
Address [A]
CEx [E]
OE# [G]
WE# [W]
R7
R6
Data [D/Q]
R11
BYTE#[F]
R5
RP# [P]
Notes:
1.
CE
low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE
X
CE0, CE1, or CE2 that disables the device.
2.
When reading the flash array a faster t
query reads, or device identifier reads).
Figure 12: 4-Word Asynchronous Page Mode Read Waveform
A[MAX:3] [A]
A[2:1] [A]
CEx [E]
OE# [G]
WE# [W]
R6
R7
D[15:0] [Q]
R5
RP# [P]
Note:
CE
low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE
X
CE0, CE1, or CE2 that disables the device.
November 2007
308551-05
R1
R1
R2
R3
R4
R16
R12
R13
(R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,
GLQV
R1
R1
R2
00
01
R3
R4
R10
R15
1
2
R8
R9
R10
high is defined at the first edge of
X
10
11
R8
R10
R9
3
4
high is defined at the first edge of
X
Datasheet
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