TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 

Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Page 9/68

Download datasheet (911Kb)Embed
PrevNext
Numonyx™ Embedded Flash Memory (J3 v. D)
Blocks are selectively and individually lockable in-system. Individual block locking uses
block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program
operations. Lock-bit configuration operations set and clear lock-bits (using the Set
Block Lock-Bit and Clear Block Lock-Bits commands).
The Status Register indicates when the WSM’s block erase, program, or lock-bit
configuration operation is finished.
The STS (STATUS) output gives an additional indicator of WSM activity by providing
both a hardware signal of status (versus software polling) and status masking
(interrupt masking for background block erase, for example). Status indication using
STS minimizes both CPU overhead and system power consumption. When configured in
level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the
WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates
that the WSM is ready for a new command, block erase is suspended (and
programming is inactive), program is suspended, or the device is in reset/power-down
mode. Additionally, the configuration command allows the STS signal to be configured
to pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design
reduces decoder logic typically required for multi-chip designs. External logic is not
required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM
module.
The BYTE# signal allows either x8 or x16 read/writes to the device:
• BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high
byte.
• BYTE#-high enables16-bit operation; address A1 becomes the lowest order
address and address A0 is not used (don’t care).
Figure 1, “Memory Block Diagram (32, 64 and 128 Mbit)” on page 10
block diagram.
When the device is disabled, with CEx at VIH and RP# at VIH, the standby mode is
enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (tPHQV) is
required from RP# going high until data outputs are valid. Likewise, the device has a
wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at
VIL, the WSM is reset and the Status Register is cleared. (see
Truth Table” on page
November 2007
308551-05
31).
shows a device
Table 15, “Chip Enable
Datasheet
9