TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup
command, the device’s read mode is automatically changed to Read Status Register
mode. After issuing the confirm command, completion of the operation is indicated by
STS (in RY/BY# mode) going high and SR7 = 1.
Blocks cannot be locked or unlocked while programming or erasing, or while the device
is suspended. Reliable block lock and unlock operations occur only when V
are valid. When V
When the set lock-bit operation is complete, SR4 should be checked for any error.
When the clear lock-bit operation is complete, SR5 should be checked for any error.
Errors bits must be cleared using the Clear Status Register command.
Block lock-bit status can be determined by first issuing the Read Device Information
command, and then reading from <block base address> + 02h. DQ0 indicates the lock
status of the addressed block (0 = unlocked, 1 = locked).
9.7.2
Configurable Block Locking
One of the unique new features on the Numonyx™ Embedded Flash Memory (J3 v. D),
non-existent on the previous generations of this product family, is the ability to protect
and/or secure the user’s system by offering multiple level of securities: Non-Volatile
Temporary; Non-Volatile Semi-Permanently or Non-Volatile Permanently. For additional
information and collateral request, please contact your filed representative.
9.7.3
OTP Protection Registers
Numonyx™ Embedded Flash Memory (J3 v. D) includes a 128-bit Protection Register
(PR) that can be used to increase the security of a system design. For example, the
number contained in the PR can be used to “match” the flash component with other
system components such as the CPU or ASIC, hence preventing device substitution.
The 128-bits of the PR are divided into two 64-bit segments:
• One segment is programmed at the Numonyx factory with a unique unalterable 64-
bit number.
• The other segment is left blank for customer designers to program as desired. Once
the customer segment is programmed, it can be locked to prevent further
programming.
9.7.4
Reading the OTP Protection Register
The Protection Register is read in Identification Read mode. The device is switched to
this mode by issuing the Read Identifier command (0090h). Once in this mode, read
cycles from addresses shown in
To return to Read Array mode, write the Read Array command (00FFh).
9.7.5
Programming the OTP Protection Register
Protection Register bits are programmed using the two-cycle Protection Program
command. The 64-bit number is programmed 16 bits at a time for word-wide
configuration and eight bits at a time for byte-wide configuration. First write the
Protection Program Setup command, 00C0h. The next write to the device will latch in
address and data and program the specified location. The allowable addresses are
shown in
Table 28, “Word-Wide Protection Register Addressing” on page 45
“Byte-Wide Protection Register Addressing” on page
Protection Program commands outside the defined PR address space will result in a
Status Register error (SR.4 will be set). Attempting to program a locked PR segment
will result in a Status Register error (SR.4 and SR.1 will be set).
Datasheet
44
Numonyx™ Embedded Flash Memory (J3 v. D)
≤ V
, block lock-bits cannot be changed.
PEN
PENLK
Table 28
or
Table 29
and V
CC
PEN
retrieve the specified information.
or
Table 29,
46. Any attempt to address
November 2007
308551-05