AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 130

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

2-wire Serial
Interface
(Byte Oriented)
130
AT94K Series FPSLIC
The 2-wire Serial Bus is a bi-directional two-wire serial communication standard. It is designed
primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two
lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs con-
nected to them. Various communication configurations can be designed using this bus.
Figure 68 shows a typical 2-wire Serial Bus configuration. Any device connected to the bus
can be Master or Slave.
Figure 68. 2-wire Serial Bus Configuration
The 2-wire Serial Interface provides a serial interface that meets the 2-wire Serial Bus specifi-
cation and supports Master/Slave and Transmitter/Receiver operation at up to 400 kHz bus
clock rate. The 2-wire Serial Interface has hardware support for the 7-bit addressing, but is
easily extended to 10-bit addressing format in software. When operating in 2-wire Serial
mode, i.e., when TWEN is set, a glitch filter is enabled for the input signals from the pins SCL
and SDA, and the output from these pins are slew-rate controlled. The 2-wire Serial Interface
is byte oriented. The operation of the serial 2-wire Serial Bus is shown as a pulse diagram in
Figure 69, including the START and STOP conditions and generation of ACK signal by the
bus receiver.
Figure 69. 2-wire Serial Bus Timing Diagram
The block diagram of the 2-wire Serial Bus interface is shown in Figure 70.
SDA
SCL
CONDITION
START
MSB
Device 1
1
2
Device 2
7
R/W
BIT
8
Device 3
ACK
9
FROM RECEIVER
ACKNOWLEDGE
.......
1
2
Device n
8
REPEATED START CONDITION
R1
ACK
9
R2
Rev. 1138F–FPSLI–06/02
STOP CONDITION
V
SCL
SDA
CC