AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 79
AT94K05AL
Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet
1.AT94K05AL.pdf
(192 pages)
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Scanning AVR RESET
Rev. 1138F–FPSLI–06/02
When no alternate port function is present, the Input Data - ID corresponds to the PINn regis-
ter value, Output Data corresponds to the PORTn register, Output Control corresponds to the
Data Direction (DDn) register, and the PuLL-up Disable (PLD) corresponds to logic expression
(DDn OR NOT(PORTBn)).
Digital alternate port functions are connected outside the dashed box in Figure 44 to make the
scan chain read the actual pin value.
Multiple sources contribute to the internal AVR reset; therefore, the AVR reset pin is not
observed. Instead, the internal AVR reset signal output from the Reset Control Unit is
observed, see Figure 45. The scanned signal is active High if AVRResetn is Low and enabled
or the device is in general reset (Resetn or power-on) or configuration download.
Figure 45. Observe-only Cell
RESET CONTROL
UNIT
Previous
From
Cell
ShiftDR
0
1
ClockDR
AT94K Series FPSLIC
D
FF1
Q
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Cell
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To System Logic
79
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