AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 45

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Memory Access Times
and Instruction
Execution Timing
Rev. 1138F–FPSLI–06/02
Data Indirect
Operand address is the contents of the X-, Y- or the Z-register.
Data Indirect with Pre-decrement
The X-, Y- or the Z-register is decremented before the operation. Operand address is the dec-
remented contents of the X, Y or the Z-register.
Data Indirect with Post-increment
The X-, Y- or the Z-register is incremented after the operation. The operand address is the
content of the X-, Y- or the Z-register prior to incrementing.
Direct Program Address, JMP and CALL
Program execution continues at the address immediate in the instruction words.
Indirect Program Addressing, IJMP and ICALL
Program execution continues at address contained by the Z-register (i.e., the PC is loaded
with the contents of the Z-register).
Relative Program Addressing, RJMP and RCALL
Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
This section describes the general access timing concepts for instruction execution and inter-
nal memory access.
The AVR CPU is driven by the XTAL1 input directly generated from the external clock crystal
for the chip. No internal clock division is used.
Figure 29 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access register file concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks and functions per power-unit.
AT94K Series FPSLIC
45