AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 136

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Master Receiver Mode
Slave Receiver Mode
136
AT94K Series FPSLIC
detailed in Table 40. The data must be loaded when TWINT is High only. If not, the access will
be discarded, and the Write Collision bit, TWWC, will be set in the TWCR register. This
scheme is repeated until a STOP condition is transmitted by writing a logic 1 to the TWSTO bit
in the TWCR register.
After a repeated START condition (state $10) the 2-wire Serial Interface may switch to the
Master Receiver mode by loading TWDR with SLA+R.
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter,
see Figure 72. The transfer is initialized as in the Master Transmitter mode. When the START
condition has been transmitted, the TWINT flag is set by the hardware. The software must
then load TWDR with the 7-bit Slave address and the data direction bit (SLA+R). The 2-wire
Serial Interrupt flag must then be cleared by software before the 2-wire Serial Transfer can
continue.
When the Slave address and the direction bit have been transmitted and an acknowledgment
bit has been received, TWINT is set again and a number of status codes in TWSR are possi-
ble. Status codes $40, $48, or $38 apply to Master mode, and status codes $68, $78, or $B0
apply to Slave mode. The appropriate action to be taken for each of these status codes is
detailed in Table 41. Received data can be read from the TWDR register when the TWINT flag
is set High by the hardware. This scheme is repeated until a STOP condition is transmitted by
writing a logic 1 to the TWSTO bit in the TWCR register.
After a repeated START condition (state $10), the 2-wire Serial Interface may switch to the
Master Transmitter mode by loading TWDR with SLA+W.
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter,
see Figure 73. To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as
follows:
Table 38. TWAR: Slave Receiver Mode Initialization
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the 2-wire Serial Interface will respond to the general
call address ($00), otherwise it will ignore the general call address.
Table 39. TWCR: Slave Receiver Mode Initialization
TWEN must be set to enable the 2-wire Serial Interface. The TWEA bit must be set to enable
the acknowledgment of the device’s own Slave address or the general call address. TWSTA
and TWSTO must be cleared.
When TWAR and TWCR have been initialized, the 2-wire Serial Interface waits until it is
addressed by its own Slave address (or the general call address if enabled) followed by the
data direction bit which must be “0” (write) for the 2-wire Serial Interface to operate in the
Slave Receiver mode. After its own Slave address and the write bit have been received, the 2-
wire Serial Interrupt flag is set and a valid status code can be read from TWSR. The status
code is used to determine the appropriate software action. The appropriate action to be taken
for each status code is detailed in Table 42. The Slave Receiver mode may also be entered if
arbitration is lost while the 2-wire Serial Interface is in the Master mode (see states $68 and
$78).
TWAR
value
TWCR
value
TWA6
Device’s own Slave address
TWINT
0
TWA5
TWEA
1
TWA4
TWSTA
0
TWA3
TWSTO
0
TWA2
TWWC
0
TWA1
TWEN
1
Rev. 1138F–FPSLI–06/02
TWA0
-
0
TWGCE
TWIE
X