mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 139

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

These register locations are not used (reserved). All unused registers and bits in this block return logic 0s
when read. Writes to these registers have no effect.
These registers are not in the on-chip map in special peripheral mode.
4.3.2.6
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Port E is associated with external bus control signals and interrupt inputs. These include mode select
(MODB/IPIPE1, MODA/IPIPE0), E clock, size (LSTRB/TAGLO), read/write (R/W), IRQ, and XIRQ.
When not used for one of these specific functions, port E pins 7:2 can be used as general-purpose I/O and
pins 1:0 can be used as general-purpose input. The port E assignment register (PEAR) selects the function
of each pin and DDRE determines whether each pin is an input or output when it is configured to be
general-purpose I/O. DDRE also determines the source of data for a read of PORTE.
Some of these pins have software selectable pull resistors. IRQ and XIRQ can only be pulled up whereas
the polarity of the PE7, PE4, PE3, and PE2 pull resistors are determined by chip integration. Please refer
to the device overview chapter (Signal Property Summary) to determine the polarity of these resistors.
A single control bit enables the pull devices for all of these pins when they are configured as inputs.
This register is not in the on-chip map in special peripheral mode or in expanded modes when the EME
bit is set. Therefore, these accesses will be echoed externally.
Freescale Semiconductor
Module Base + 0x0008
Starting address location affected by INITRG register setting.
Pin Function
Alternate
Reset
W
R
Port E Data Register (PORTE)
NOACC
It is unwise to write PORTE and DDRE as a word access. If you are
changing port E pins from being inputs to outputs, the data may have extra
transitions during the write. It is best to initialize PORTE before enabling as
outputs.
Bit 7
0
7
= Unimplemented or Reserved
or CLKTO
or IPIPE1
MODB
6
0
6
Figure 4-10. Port E Data Register (PORTE)
MC9S12C-Family / MC9S12GC-Family
or IPIPE0
MODA
5
0
5
Rev 01.23
NOTE
ECLK
4
0
4
u = Unaffected by reset
or TAGLO
LSTRB
Chapter 4 Multiplexed External Bus Interface (MEBIV3)
3
3
0
R/W
2
2
0
Bit 1
IRQ
u
1
XIRQ
Bit 0
u
0
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