mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 355
mc9s12c32mpb16
Manufacturer Part Number
mc9s12c32mpb16
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12C32MPB16.pdf
(680 pages)
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12.3.2.3
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
Read: anytime
Write: anytime
Freescale Semiconductor
Module Base + 0x0002
PPOL3
PPOL2
PPOL1
PPOL0
Reset
Field
3
2
1
0
W
R
Pulse Width Channel 3 Polarity
0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 2 Polarity
0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 1 Polarity
0 PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 0 Polarity
0 PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached.
PWM Clock Select Register (PWMCLK)
0
0
7
Register bits PCLK0 to PCLK5 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
= Unimplemented or Reserved
0
0
6
Table 12-3. PWMPOL Field Descriptions (continued)
Figure 12-5. PWM Clock Select Register (PWMCLK)
PCLK5
MC9S12C-Family / MC9S12GC-Family
0
5
PCLK4
Rev 01.23
NOTE
0
4
Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
Description
PCLK3
0
3
PCLK2
0
2
PCLK1
0
1
PCLK0
0
0
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