mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 282

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.4.10.2
The MCU requires an external interrupt or an external reset in order to wake-up from stop mode.
If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all
configuration bits in the register space to its default settings and will perform a maximum of 50 clock
check_windows (see
the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the
normal reset vector. Full stop mode is exited and the MCU is in run mode again.
If the MCU is woken-up by an interrupt, the CRG will also perform a maximum of 50 clock
check_windows (see
CRG will release all system and core clocks and will continue with normal operation. If all clock checks
within the timeout-window are failing, the CRG will switch to self-clock mode or generate a clock monitor
reset (CMRESET) depending on the setting of the SCME bit.
Because the PLL has been powered-down during stop mode the PLLSEL bit is cleared and the MCU runs
on OSCCLK after leaving stop mode. The software must manually set the PLLSEL bit again, in order to
switch system and core clocks to the PLLCLK.
9.5
This section describes how to reset the CRGV4 and how the CRGV4 itself controls the reset of the MCU.
It explains all special reset requirements. Because the reset generator for the MCU is part of the CRG, this
section also describes all automatic actions that occur during or as a result of individual reset conditions.
The reset values of registers and signals are provided in
282
CME
1
SCME
1
Resets
Wake-up from Full Stop (PSTP=0)
SCMIE
In full stop mode, the clock monitor is disabled and any loss of clock will
not be detected.
1
Table 9-12. Outcome of Clock Loss in Pseudo-Stop Mode (continued)
Section 9.4.4, “Clock Quality
Section 9.4.4, “Clock Quality
Clock failure -->
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– SCMIF set.
SCMIF generates Self-Clock Mode wakeup interrupt.
– Exit Pseudo-Stop Mode in SCM using PLL clock (f
– Continue to perform a additional Clock Quality Checks until OSCCLK
is o.k. again.
MC9S12C-Family / MC9S12GC-Family
Rev 01.23
NOTE
Checker”). If the clock quality check is successful, the
Checker”). After completing the clock quality check
Section 9.3, “Memory Map and Register
CRG Actions
SCM
) as system clock,
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