mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 425

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

14.4.2
The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI
data in a slave mode. For these simpler devices, there is no serial data out pin.
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for
several slaves to receive the same transmission from a master, although the master would not receive return
information from all of the receiving slaves.
If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SCK input cause the data
at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the
serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to
be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift
into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA
is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data
output pin. After the eighth shift, the transfer is considered complete and the received data is transferred
into the SPI Data Register. To indicate transfer is complete, the SPIF flag in the SPI Status Register is set.
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SCK Clock
In slave mode, SCK is the SPI clock input from the master.
MISO and MOSI Pins
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI)
is determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2.
SS Pin
must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is
forced into idle state.
output pin is high impedance, and, if SS is low the first bit in the SPI Data Register is driven out of
the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is
ignored and no internal shifting of the SPI shift register takes place.
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI
The SS input also controls the serial data output pin, if SS is high (not selected), the serial data
Slave Mode
When peripherals with duplex capability are used, take care not to
simultaneously enable two receivers whose serial outputs drive the same
system slave’s serial data output line.
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0 and
BIDIROE with SPC0 set in slave mode will corrupt a transmission in
progress and has to be avoided.
MC9S12C-Family / MC9S12GC-Family
Rev 01.23
NOTE
NOTE
Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
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