mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 155

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.4.3.2
There are two special operating modes that correspond to normal operating modes. These operating modes
are commonly used in factory testing and system development.
4.4.3.2.1
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does
not fetch the reset vector and execute application code as it would in other modes. Instead the active
background mode is in control of CPU execution and BDM firmware is waiting for additional serial
commands through the BKGD pin. When a serial command instructs the MCU to return to normal
execution, the system will be configured as described below unless the reset states of internal control
registers have been changed through background commands after the MCU was reset.
There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional
I/O pins that are configured as high-impedance inputs with internal pull resistors disabled; however,
writing to the mode select bits in the MODE register (which is allowed in special modes) can change this
after reset. All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-
impedance inputs with internal pull resistors enabled. PE4/ECLK is configured as the E clock output in
this mode.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in
single chip mode does not change the operation of the associated Port E pins.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
4.4.3.2.2
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. In special test mode, the write protection of many control
bits is lifted so that they can be thoroughly tested without needing to go through reset.
4.4.3.3
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip
peripherals.
4.4.3.3.1
This mode is intended for factory testing of the MCU. In this mode, the CPU is inactive and an external
(tester) bus master drives address, data and bus control signals in through Ports A, B and E. In effect, the
whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster testing of
on-chip memory and peripherals than previous testing methods. Since the mode control register is not
accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different
Freescale Semiconductor
Special Operating Modes
Test Operating Mode
Special Single-Chip Mode
Special Test Mode
Peripheral Mode
MC9S12C-Family / MC9S12GC-Family
Rev 01.23
Chapter 4 Multiplexed External Bus Interface (MEBIV3)
155