mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 284

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted
synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven
low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
9.5.1
The CRGV4 generates a clock monitor reset in case all of the following conditions are true:
The reset event asynchronously forces the configuration registers to their default settings (see
“Memory Map and Register
doesn’t change the state of the CME bit, because it has already been set). As a consequence, the CRG
immediately enters self-clock mode and starts its internal reset sequence. In parallel the clock quality
check starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to
OSCCLK and leaves self-clock mode. Because the clock quality checker is running in parallel to the reset
generator, the CRG may leave self-clock mode while completing the internal reset sequence. When the
reset sequence is finished the CRG checks the internally latched state of the clock monitor fail circuit. If a
clock monitor fail is indicated processing begins by fetching the clock monitor reset vector.
9.5.2
When COP is enabled, the CRG expects sequential write of 0x0055 and 0x00AA (in this order) to the
ARMCOP register during the selected time-out period. As soon as this is done, the COP time-out period
restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x0055
or 0x00AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled
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•
•
•
Clock monitor is enabled (CME=1)
Loss of clock is detected
Self-clock mode is disabled (SCME=0)
Clock Monitor Reset
Computer Operating Properly Watchdog (COP) Reset
SYSCLK
RESET
Definition”). In detail the CME and the SCME are reset to logical ‘1’ (which
possibly
SYSCLK
not
running
MC9S12C-Family / MC9S12GC-Family
CRG drives RESET pin low
) (
Figure 9-25. RESET Timing
128+n cycles
with n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
Rev 01.23
) (
)
(
RESET pin
released
64 cycles
)
(
possibly
RESET
driven low
externally
)
(
Freescale Semiconductor
Section 9.3,