mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 258

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.2.4
This register provides CRG status bits and flags.
Read: anytime
Write: refer to each bit for individual write conditions
258
Module Base + 0x0003
1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset.
LOCKIF
TRACK
Reset
PORF
LOCK
Field
LVRF
RTIF
7
6
5
4
3
2
W
R
RTIF
Real-Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
Power-on Reset Flag — PORF is set to 1 when a power-on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power-on reset has not occurred.
1 Power-on reset has occurred.
Low-Voltage Reset Flag — If low voltage reset feature is not available (see the device overview chapter), LVRF
always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1.
Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
Lock Status Bit — LOCK reflects the current state of PLL lock condition. This bit is cleared in self-clock mode.
Writes have no effect.
0 PLL VCO is not within the desired tolerance of the target frequency.
1 PLL VCO is within the desired tolerance of the target frequency.
Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode.
Writes have no effect.
0 Acquisition mode status.
1 Tracking mode status.
CRG Flags Register (CRGFLG)
0
7
= Unimplemented or Reserved
Note 1
PORF
6
Figure 9-7. CRG Flag Register (CRGFLG)
Table 9-2. CRGFLG Field Descriptions
Note 2
LVRF
MC9S12C-Family / MC9S12GC-Family
5
LOCKIF
Rev 01.23
0
4
Description
LOCK
0
3
TRACK
0
2
Freescale Semiconductor
SCMIF
0
1
SCM
0
0