mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 322

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
Read: Anytime when TXEx flag is set (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register
Write: Anytime when TXEx flag is set (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register
10.3.3.5
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see
“MSCAN Control Register 0
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
322
Module Base + 0xXXXD
Module Base + 0xXXXE
Module Base + 0xXXXF
Reset:
Reset:
Reset:
W
W
W
R
R
R
Time Stamp Register (TSRH–TSRL)
TSR15
PRIO7
TSR7
0
7
7
x
7
x
Figure 10-36. Time Stamp Register — High Byte (TSRH)
Figure 10-37. Time Stamp Register — Low Byte (TSRL)
Figure 10-35. Transmit Buffer Priority Register (TBPR)
TSR14
PRIO6
TSR6
6
0
6
x
6
x
(CANCTL0)”). In case of a transmission, the CPU can only read the time
MC9S12C-Family / MC9S12GC-Family
TSR13
PRIO5
TSR5
0
5
5
x
5
x
Section 10.3.2.7, “MSCAN Transmitter Flag Register
Section 10.3.2.7, “MSCAN Transmitter Flag Register
(CANTBSEL)”).
(CANTBSEL)”).
Rev 01.23
TSR12
PRIO4
TSR4
4
0
4
x
4
x
TSR11
PRIO3
TSR3
0
x
x
3
3
3
TSR10
PRIO2
TSR2
2
0
2
x
2
x
Freescale Semiconductor
PRIO1
TSR9
TSR1
Section 10.3.2.11,
Section 10.3.2.11,
Section 10.3.2.1,
0
x
x
1
1
1
PRIO0
TSR8
TSR0
0
0
0
x
0
x