mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 261

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mc9s12c32mpb16

Manufacturer Part Number
mc9s12c32mpb16
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
9.3.2.7
This register controls the PLL functionality.
Read: anytime
Write: refer to each bit for individual write conditions
Freescale Semiconductor
Module Base + 0x0006
COPWAI
RTIWAI
PLLON
Reset
CWAI
Field
Field
CME
2
1
0
7
6
W
R
CME
Core Stops in Wait Mode Bit — Write: anytime
0 Core clock keeps running in wait mode.
1 Core clock stops in wait mode.
RTI Stops in Wait Mode Bit — Write: anytime
0 RTI keeps running in wait mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.
COP Stops in Wait Mode Bit — Normal modes: Write once —Special modes: Write anytime
0 COP keeps running in wait mode.
1 COP stops and initializes the COP dividers whenever the part goes into wait mode.
Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self-clock
Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality this could cause
Note: In Stop Mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss
Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self-clock mode, the PLL is turned on, but the
PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1.
0 PLL is turned off.
1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically.
CRG PLL Control Register (PLLCTL)
1
7
mode.
unpredictable operation of the MCU.
of clock will not be detected.
= Unimplemented or Reserved
PLLON
1
6
Table 9-4. CLKSEL Field Descriptions (continued)
Figure 9-10. CRG PLL Control Register (PLLCTL)
Table 9-5. PLLCTL Field Descriptions
AUTO
MC9S12C-Family / MC9S12GC-Family
1
5
Rev 01.23
ACQ
1
4
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Description
Description
0
0
3
PRE
0
2
PCE
0
1
SCME
1
0
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