mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 453

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
CLK[1:0]
PAMOD
PEDGE
PAOVI
PAEN
Field
PAI
3:2
6
5
4
1
0
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table
0 Event counter mode.
1 Gated time accumulation mode.
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
Clock Select Bits — Refer to
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
edge on IOC7 sets the PAIF flag.
on IOC7 sets the PAIF flag.
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
15-18.
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Table 15-17. PACTL Field Descriptions
MC9S12C-Family / MC9S12GC-Family
Table
Table 15-18. Pin Action
15-19.
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
Rev 01.23
NOTE
Table
Description
15-18.
Falling edge
Rising edge
Pin Action
Chapter 15 Timer Module (TIM16B8CV1) Block Description
453