mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 159

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mc9s12c32mpb16

Manufacturer Part Number
mc9s12c32mpb16
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
5.2
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and
XIRQ pin data.
5.3
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
5.3.1
5.3.2
5.3.2.1
Read: See individual bit descriptions
Write: See individual bit descriptions
Freescale Semiconductor
Module Base + 0x0015
Starting address location affected by INITRG register setting.
Reset
W
R
External Signal Description
Memory Map and Register Definition
Address
0x0015
0x0016
0x001F
Offset
Module Memory Map
Register Descriptions
Interrupt Test Control Register
0
0
7
Interrupt Test Control Register (ITCR)
Interrupt Test Registers (ITEST)
Highest Priority Interrupt (Optional) (HPRIO)
= Unimplemented or Reserved
0
0
6
Figure 5-2. Interrupt Test Control Register (ITCR)
MC9S12C-Family / MC9S12GC-Family
0
0
5
Table 5-1. INT Memory Map
WRTINT
Rev 01.23
0
4
Use
ADR3
1
3
Chapter 5 Interrupt (INTV1) Block Description
ADR2
1
2
ADR1
1
1
Access
R/W
R/W
R/W
ADR0
1
0
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