mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 513

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

18.3.2.6
The FSTAT register defines the status of the Flash command controller and the results of command
execution.
In normal modes, bits CBEIF, PVIOL, and ACCERR are readable and writable, bits CCIF and BLANK
are readable and not writable, remaining bits, including FAIL and DONE, read 0 and are not writable. In
special modes, FAIL is readable and writable while DONE is readable but not writable. FAIL must be clear
in special modes when starting a command write sequence.
Freescale Semiconductor
Module Base + 0x0005
Reset
CBEIF
Field
CCIF
7
6
W
R
CBEIF
Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command
buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing
a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned
word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause
the ACCERR flag in the FSTAT register to be set. Writing a 0 to CBEIF outside of a command write sequence
will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to
generate an interrupt request (see
0 Buffers are full
1 Buffers are ready to accept a new command
Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The
CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending
commands. The CCIF flag does not set when an active commands completes and a pending command is
fetched from the command buffer. Writing to the CCIF flag has no effect. The CCIF flag is used together with the
CCIE bit in the FCNFG register to generate an interrupt request (see
0 Command in progress
1 All commands are completed
1. Allowed transitions marked with X.
Flash Status Register (FSTAT)
1
7
Protection
Scenario
From
6
7
= Unimplemented or Reserved
CCIF
1
6
Table 18-12. Flash Protection Scenario Transitions
Figure 18-10. Flash Status Register (FSTAT)
0
X
Table 18-13. FSTAT Field Descriptions
PVIOL
MC9S12C-Family / MC9S12GC-Family
0
5
X
X
1
Figure
ACCERR
X
18-26).
2
Rev 01.23
To Protection Scenario
0
4
Description
X
X
3
0
0
3
X
X
4
Chapter 18 32 Kbyte Flash Module (S12FTS32KV1)
(1)
Figure
X
5
BLANK
0
2
18-26).
X
X
6
FAIL
0
1
X
7
DONE
1
0
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