mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 273

• Manufacturer Part Number: mc9s12c32mpb16
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

If the PRE bit is set, the RTI will continue to run in pseudo-stop mode.
9.4.7
9.4.7.1
The CRGV4 block behaves as described within this specification in all normal modes.
9.4.7.2
The VCO has a minimum operating frequency, f
to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO
running at minimum operating frequency; this mode of operation is called self-clock mode. This requires
CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self-clock mode, the
PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically
select OSCCLK to be the system clock and return to normal mode. See
Checker” for more information on entering and leaving self-clock mode.
Freescale Semiconductor
Modes of Operation
Normal Mode
Self-Clock Mode
gating condition
OSCCLK
= Clock Gate
STOP(PSTP,PRE),
WAIT(RTIWAI),
RTI enable
MC9S12C-Family / MC9S12GC-Family
Figure 9-22. Clock Chain for RTI
÷
÷
÷
÷
÷
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2
2
2
2
2
2
÷
SCM
Rev 01.23
1024
.
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
. If the external clock frequency is not available due
RTR[6:4]
0:1:0
0:0:1
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
0:0:0
COUNTER (RTR[3:0])
4-BIT MODULUS
Section 9.4.4, “Clock Quality
RTI TIMEOUT
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