mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 121
mt9074ap1
Manufacturer Part Number
mt9074ap1
Description
T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT9074AP1.pdf
(151 pages)
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Per Channel Transmit Signaling (Pages 5 and 6) (E1)
Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit Signaling
Control Words for Channel Associated Signaling (CAS) channels 2 to 16 and 18 to 32 respectively. Table 132
illustrates the mapping between the addresses of these pages and the CAS channel numbers. Control of these bits
for any one channel is through the processor or controller port when the Per Time Slot Control bit RPSIG bit is high.
Table 133 describes bit allocation within each of these registers.
Page 5 Address:
Equivalent CAS
channel
Page 6 Address:
Equivalent CAS
channel
Bit
7
6
5
4
3
2
1
0
Table 131 - Page 5, 6 Address Mapping to CAS Signaling Channels (E1)
PRBSMFOFOL
FERROL
PRBSOL
FEBEOL
CRCOL
BPVOL
Name
- - -
- - -
0
1
0
17
1
2
1
18
Table 130 - Overflow Reporting Latch
2
3
2
19
Errored Frame Alignment Signal Counter Overflow Latch. This bit is
set when the errored frame alignment signal counter overflows. It is
cleared after being read.
CRC Error Counter Overflow Latch. This bit is set when the crc error
counter overflows. It is cleared after being read.
E Bit Counter Overflow Latch. This bit is set when E bit counter
overflows. It is cleared after being read.
Bipolar Violation Counter Overflow Latch. This bit is set when the
bipolar violation counter overflows. It is cleared after being read.
Pseudo Random Bit Sequence Error Counter Overflow Latch. This
bit is set when the PRBS error counter overflows. It is cleared after being
read.
Pseudo Random Bit Sequence Multiframe Counter Overflow Latch.
This bit is set when the multiframe counter attached to the PRBS error
counter overflows. It is cleared after being read
Unused.
(Page 4, Address 1FH) (E1)
3
4
3
20
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Functional Description
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Data Sheet
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