mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 16

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

MT9074
Data Sheet
The MT9074 in E1 mode operates as an advanced PCM30 framer with an on-chip Line Interface Unit (LIU) that
meets or supports the latest ITU-T Recommendations for PCM30 and ISDN primary rate including G.703, G.704,
G.706, G.775, G.796, G.732, G.823 and I.431. It also meets or supports the layer 1 requirements of ETSI ETS 300
011, ETS 300 166, ETS 300 233 and BS6450.
The Line Interface Unit (LIU) of the MT9074 interfaces the digital framer functions to either the DS1 (T1 mode) or
PCM30 (E1 mode) transformer-isolated four wire line. The transmit portion of the MT9074 LIU consists of a digital
buffer, a digital-to-analog converter, and a differential line driver. The receiver portion of the MT9074 LIU consists of
an input signal peak detector, an optional equalizer, a smoothing filter, data and clock slicers and a clock extractor.
System timing may be slaved to the line, operated in free-run mode or controlled by an external timing source. In T1
mode the MT9074 contains a PLL which always generates the transmit timing for the LIU. In E1 mode the LIU also
contains a Jitter Attenuator (JA), which can be included in either the transmit or receive path. The MT9074 will
attenuate jitter from 2.5 Hz and roll-off at a rate of 20 dB/decade. The intrinsic jitter is less than 0.02 UI. The PLL
output (@1.544 MHz for T1 mode and @2.048 MHz for E1 mode) clocks out the transmit line data.
To accommodate some special applications, the MT9074 also supports a digital framer only mode by providing
direct access to the transmit and receive data in digital format, i.e., by-passing the analog LIU front-end.
The digital portion of the MT9074 connects selected channels of an incoming stream of time multiplexed 2.048
Mbit/s PCM channels to the transmit payload of either the T1 or E1 trunk, while the receive payload is connected to
the ST-BUS 2.048 Mbit/s backplane bus for both data and signaling with channel times and the frame boundary
synchronous to the transmit side. Control, reporting and conditioning of the line is implemented via a parallel
microprocessor interface.
The MT9074 has a comprehensive suite of status, alarm, performance monitoring and reporting features. These
include counters for BPVs, CRC errors, F-bit errors (T1 only), E-bit errors (E1 only), errored frame alignment
signals (E1 only), BERT, OOF (T1 only), and RAI and continuous CRC errors (E1 only). Also, included are
transmission error insertion for BPVs, CRC-6 errors (T1 only), CRC-4 errors (E1 only), framing bit errors (T1 only),
frame and non-frame alignment signal errors (E1 only), payload errors and loss of signal errors. A built-in PRBS
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generator (2
-1) can be connected to any combination of outgoing channels; an equivalent PRBS error detector
can be independently connected to any combination of receive channels.
A complete set of loopbacks has been implemented, which include digital, remote, ST-BUS, payload, local, metallic
and remote time slot.
The MT9074 also provides a comprehensive set of maskable interrupts. Interrupt sources consist of
synchronization status, alarm status, counter indication and overflow, timer status, slip indication, maintenance
functions and receive channel associated signaling bit changes.
In T1 mode the framer operates in any one of the framing modes: D4, SLC-96 and Extended Superframe (ESF).
The ESF FDL bits of the MT9074 can be accessed either through the data link pins TxDL, RxDL, RxDLCLK and
TxDLCLK, or through internal registers for Bit Oriented Messages, or through a built-in HDLC. A second HDLC may
be connected to DS1 channel 24 for the ISDN Primary Rate signaling applications.
In E1 mode the MT9074 operates in either termination or transparent modes selectable via software control. In the
termination mode the CRC-4 calculation is performed as part of the framing algorithm. In the transmit transparent
mode, no framing or signaling is imposed on the data transmit from DSTi on the line. In addition, the MT9074
optionally allows the data link maintenance channel to be modified and updates the CRC-4 remainder bits to reflect
the modification. All channel, framing and signaling data passes through the device unaltered. This is useful for
intermediate point applications of a PCM30 link where the data link data is modified, but the error information
transported by the CRC-4 bits must be passed to the terminating end. In the receive transparent mode, the
received line data is channelled to DSTo with framing operations disabled, consequently, the data passes through
the slip buffer and drives DSTo with an arbitrary alignment.
In E1 mode the S
bits can be accessed by the MT9074 in the following three ways:
a
•
Programming a register;
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