mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 32

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

receive side, the transmit Y-bit is zero; when CAS multiframing is not acquired, the transmit Y-bit is one. Bits 5, 7
and 8 (usually designated X) are spare bits and are normally set to one if not used.
Time slot 16 of the remaining 15 basic frames of the CAS multiframe (i.e., basic frames 1 to 15) are reserved for the
ABCD signaling bits for the 30 payload channels. The most significant nibbles are reserved for channels 1 to 15 and
the least significant nibbles are reserved for channels 16 to 30. That is, time slot 16 of basic frame 1 has ABCD for
channel 1 and 16, time slot 16 of basic frame 2 has ABCD for channel 2 and 17, through to time slot 16 of basic
frame 15 has ABCD for channel 15 and 30.
MT9074 Access and Control
The Control Port Interface
The control and status of the MT9074 is achieved through a non-multiplexed parallel microprocessor port. The
parallel port may be configured for Motorola style control signals (by setting pin INT/MOT low) or Intel style control
signals (by setting pin INT/MOT high).
Control and Status Register Access
The controlling microprocessor gains access to specific registers of the MT9074 through a two step process. First,
writing to the Command/Address Register (CAR) selects one of the 15 pages of control and status registers (CAR
address: AC4 = 0, AC3-AC0 = don't care, CAR data D7 - D0 = page number). Second, each page has a maximum
of 16 registers that are addressed on a read or write to a non-CAR address (non-CAR: address AC4 = 1, AC3-AC0
= register address, D7-D0 = data). Once a page of memory is selected, it is only necessary to write to the CAR
when a different page is to be accessed. See the AC Electrical Characteristics section.
Please note that for microprocessors with read/write cycles less than 200 ns, a wait state or a dummy operation (for
C programming) between two successive read/write operations to the HDLC FIFO is required.
Table 13 associates the MT9074 control and status pages with access and page descriptions.
00000001 (01H)
00000010 (02H)
00000011 (03H)
00000100 (04H)
00000101 (05H)
00000110 (06H)
00000111 (07H)
00001000 (08H)
00001001 (09H)
00001010 (0AH)
00001011 (0BH)
00001100 (0CH)
Page Address
D
7
- D
0
Master
Control
Master
Per Channel Transmit Signaling
Per Channel Transmit Signaling
Per Time Slot Control
Per Time Slot Control
Per Channel Receive Signaling
Per Channel Receive Signaling
HDLC0 Control and Status
HDLC1 Control and Status
Status
Register Description
Table 13 - Page Summary
Zarlink Semiconductor Inc.
MT9074
32
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R/W
R/W
Processor
Access
CSTi
CSTi
---
CSTo
CSTo
---
- - -
- - -
- - -
- - -
Data Sheet
ST-BUS
Access