mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 40

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

MT9074
Data Sheet
receive bit rates and enables can operate independently. In MT9074 the transceiver can operate at a continuous
rate independent of RXcen and TXcen (free run mode) by setting the Frun bit of Control Register 1.
Received packets from the serial interface are sectioned into bytes by an HDLC receiver that detects flags, checks
for go-ahead signals, removes inserted zeros, performs a cyclical redundancy check (CRC) on incoming data, and
monitors the address if required. Packet reception begins upon detection of an opening flag. The resulting bytes are
concatenated with two status bits (RQ9, RQ8) and placed in a receiver first-in-first-out (Rx FIFO); a buffer register
that generates status and interrupts for microprocessor read control.
In conjunction with the control circuitry, the microprocessor writes data bytes into a Tx buffer register (Tx FIFO) that
generates status and interrupts. Packet transmission begins when the microprocessor writes a byte to the Tx FIFO.
Two status bits are added to the Tx FIFO for transmitter control of frame aborts (FA) and end of packet (EOP) flags.
Packets have flags appended, zeros inserted, and a CRC, also referred to as frame checking sequence (FCS),
added automatically during serial transmission. When the Tx FIFO is empty and finished sending a packet,
Interframe Time Fill bytes (continuous flags (7E hex)), or Mark Idle (continuous ones) are transmitted to indicate
that the channel is idle.
HDLC Transmitter
Following initialization and enabling, the transmitter is in the Idle Channel state (Mark Idle), continuously sending
ones. Interframe Time Fill state (Flag Idle) is selected by setting the Mark idle bit in Control Register 1 high.
NOTE: If the MT9074A HDLC transmitter is set up in the Interframe Time Fill state (bit 2, Mark-Idle=1, page B
or C, address 13H), then it will occasionally (less than 1% of the time) fail to transmit the opening flag when
it is changed from the disabled state to the enabled state (bit 5 TxEN changed from 0 to1). A missing
opening flag will cause the packet to be lost at the receiving end.
This problem only affects the first packet transmitted after the HDLC transmitter is enabled. Subsequent
packets are unaffected.
The Transmitter remains in either of these two states until data is written to the Tx FIFO. Control Register 1 bits
EOP (end of packet) and FA (Frame Abort) are set as status bits before the microprocessor loads 8 bits of data into
the 10 bit wide FIFO (8 bits data and 2 bits status). To change the tag bits being loaded in the FIFO, Control
Register 1 must be written to before writing to the FIFO. However, EOP and FA are reset after writing to the TX
FIFO. The Transmit Byte Count Register may also be used to tag an end of packet. The register is loaded with the
number of bytes in the packet and decrements after every write to the Tx FIFO. When a count of one is reached,
the next byte written to the FIFO is tagged as an end of packet. The register may be made to cycle through the
same count if the packets are of the same length by setting Control Register 2 bit Cycle.
If the transmitter is in the Idle Channel state when data is written to the Tx FIFO, then an opening flag is sent and
data from Tx FIFO follows. Otherwise, data bytes are transmitted as soon as the current flag byte has been sent. Tx
FIFO data bytes are continuously transmitted until either the FIFO is empty or an EOP or FA status bit is read by the
transmitter. After the last bit of the EOP byte has been transmitted, a 16-bit FCS is sent followed by a closing flag.
When multiple packets of data are loaded into Tx FIFO, only one flag is sent between packets.
Frame aborts (the transmission of 7F hex), are transmitted by tagging a byte previously written to the Tx FIFO.
When a byte has an FA tag, then an FA is sent instead of that tagged byte. That is, all bytes previous to but not
including that byte are sent. After a Frame Abort, the transmitter returns to the Mark Idle or Interframe Time Fill
state, depending on the state of the Mark idle control bit.
Tx FIFO underrun will occur if the FIFO empties and the last byte did not have either an EOP or FA tag. A frame
abort sequence will be sent when an underrun occurs.
40
Zarlink Semiconductor Inc.